SAR ADC Noise Shaping Through Digital Residual Error Feedback
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Solution Overview
Problem
Successive approximation register (SAR) analog-to-digital converters (ADCs) face challenges in enhancing resolution due to residual error left after conversion, with existing noise-shaping techniques either impacting efficiency or requiring sub-ranging architectures that struggle with gain alignment.
Innovation Solution
Implementing a SAR ADC with a digital filter for noise shaping, where residual error is processed through a digital filter to improve resolution, using a capacitor array and comparator to generate digital signals that are then filtered and fed back to the sampling node for subsequent conversion phases, effectively modulating the quantization noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If noise-shaping techniques are applied to enhance SAR ADC resolution, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the ADC operation into distinct phases: a first conversion phase that generates an initial digital output, and a second conversion phase that processes residual error. This segmentation allows noise shaping to be applied selectively without requiring complete architectural redesign, thus improving resolution while controlling complexity
Solution Approach 2:
The patent introduces a residual error processing circuit as an intermediary component that takes the residual error from the first conversion phase and generates a second digital output. This intermediary structure enables noise shaping functionality without directly complicating the core SAR ADC architecture, resolving the contradiction between enhanced precision and device complexity
2Measurement precision
If sub-ranging architectures are used for noise shaping, then measurement precision is improved, but gain alignment becomes more difficult
Solution Approach 1:
The patent implements feedback by using the residual error from the first conversion phase as an input to the second conversion phase. This feedback mechanism allows the system to correct quantization noise systematically without requiring precise gain alignment between separate sub-ranging stages, thus improving measurement precision while avoiding gain alignment difficulties
Solution Approach 2:
The patent uses a simplified copy of the SAR ADC structure for the second conversion phase, which processes the residual error in the same manner as the first phase. This copying approach ensures consistent gain characteristics between phases, eliminating gain alignment issues while achieving noise shaping for improved precision
Data Source
AI summary
Certain aspects of the present disclosure provide a successive approximation register (SAR) analog-to-digital converter (ADC) implemented with a digital filter for noise shaping. For example, certain aspects provide a circuit for analog-to-digital conversion having: a first digital-to-analog converter (DAC) having an output coupled to a sampling node; a comparator having an input coupled to the sampling node; SAR logic having an input coupled to an output of the comparator and at least one output coupled to an input of the first DAC; a quantizer configured to generate a first digital signal representing a voltage at the sampling node; a digital filter configured to apply a filter to the first digital signal; and a second DAC configured to generate an analog signal representing the filtered first digital signal and provide the analog signal to the sampling node.