Split-Capacitor SAR ADC Switching for Lower Nonlinearity
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Solution Overview
Problem
Successive approximation register (SAR) analog-to-digital converters suffer from nonlinear errors due to capacitance mismatch in capacitor arrays, leading to reduced accuracy and linearity in analog-to-digital conversion.
Innovation Solution
The implementation of a 3-bit split capacitor SAR analog-to-digital converter with a switch circuit and control logic circuit that alternates the connection of two capacitor arrays to the comparator during sampling periods, using different voltage settings to reduce voltage errors and nonlinearity errors, and employing a uniform switching sequence for the switching signal between two levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If capacitor arrays are used for analog-to-digital conversion in SAR ADC, then power consumption is reduced and portability is improved, but nonlinearity error increases due to capacitance mismatch
Solution Approach 1:
The capacitor array is divided into two separate capacitor arrays (first capacitor array and second capacitor array). Each array processes one input signal independently, and their results are combined. This segmentation allows independent optimization and reduces the impact of capacitance mismatch on overall accuracy while maintaining low power consumption characteristics of SAR ADC.
Solution Approach 2:
The patent combines the conversion results from two separate capacitor arrays through an adding circuit. By merging the outputs of two independent conversion processes, the system achieves improved linearity and reduced nonlinearity error while maintaining the power efficiency of the SAR ADC architecture.
2Adaptability or versatility
If capacitor arrays are used for analog-to-digital conversion, then the converter is suitable for mobile devices, but linearity is reduced due to capacitance mismatch
Solution Approach 1:
The system segments the conversion process into two parallel paths using separate capacitor arrays, each handling one input signal. This segmentation isolates the capacitance mismatch issues in each array, preventing cumulative nonlinearity effects while maintaining the compact, low-power design suitable for mobile devices.
Solution Approach 2:
The control logic circuit coordinates the switching and timing of both capacitor arrays and the adding circuit, ensuring synchronized operation. This control mechanism provides system-level feedback and coordination that optimizes the overall conversion process, improving linearity through precise timing and sequence control.
3Measurement precision
If switching signal alternates between two levels according to uniform sequence, then nonlinearity error is reduced, but device complexity increases
Solution Approach 1:
The switching signal alternates periodically between two levels according to a uniform sequence, creating a regular, predictable pattern of operation. This periodic switching enables the two capacitor arrays to be systematically activated and combined, reducing nonlinearity error through consistent, repeating operation cycles that are easier to control and predict.
Solution Approach 2:
The system dynamically switches between two operational states (switching signal at first level or second level) to alternate which capacitor array is active. This dynamic switching allows the system to adapt its configuration periodically, optimizing performance by reducing nonlinearity while the uniform sequence keeps the control logic manageable.
Data Source
AI summary
An analog-to-digital converter includes a switch circuit, a first capacitor array, a second capacitor array and a comparator. A method of operating the analog-to-digital converter includes switching a swap signal to a first level in a first sampling period for the switch circuit to couple the first capacitor array to a first input terminal of the comparator and a first signal source, and couple the second capacitor array to a second input terminal of the comparator and a second signal source, and switching the swap signal to a second level in a second sampling period for the switch circuit to couple the first capacitor array to the second input terminal of the comparator and the second signal source, and couple the second capacitor array to the first input terminal of the comparator and the first signal source.