SAR ADC Offset Mitigation Using CDAC Charge Injection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current offset mitigation techniques in analog-to-digital converters (ADCs) increase loading and circuit size, limiting operating speed and resolution due to comparator mismatch errors.
Innovation Solution
The use of capacitor digital-to-analog converter (CDAC) circuitry to inject an offset charge into the comparator circuitry of the ADC, compensating for mismatch errors without additional loading or calibration circuits, thereby enhancing operating speed and reducing circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If additional calibration circuits are used to mitigate offset errors, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The CDAC circuitry is designed to perform dual functions: its primary function of converting digital values to analog voltages during the conversion phase, and a secondary function of injecting offset compensation charges during the calibration phase. By making the existing CDAC circuitry multi-functional, the patent eliminates the need for separate calibration circuits while maintaining offset error mitigation capabilities, thus improving measurement precision without increasing device complexity
Solution Approach 2:
The CDAC circuitry compensates for its own offset errors by injecting calibration charges into the comparator during the calibration phase. This self-service mechanism allows the circuit to correct its own mismatches without requiring external calibration circuits, thereby maintaining high measurement precision while avoiding additional circuit complexity
2Measurement precision
If additional calibration circuits are used to mitigate offset errors, then measurement precision is improved, but productivity decreases
Solution Approach 1:
The CDAC circuitry performs both conversion and calibration functions, eliminating the need for separate calibration circuits that would add to the overall circuit complexity and signal path length. This multi-functionality allows the ADC to maintain high operating speeds while achieving accurate offset compensation through the same circuitry used for normal conversion operations
Solution Approach 2:
The patent extracts the offset calibration function from separate calibration circuits and integrates it into the existing CDAC circuitry. By taking out the calibration function and combining it with the conversion function in a single circuit block, the patent reduces the overall circuit complexity and signal processing path, thereby maintaining high productivity and operating speed while achieving precise offset mitigation
3Measurement precision
If comparator loading is increased to mitigate offset, then measurement precision is improved, but productivity decreases
Solution Approach 1:
The patent employs periodic action by alternating between calibration phases and conversion phases. During the calibration phase, the CDAC circuitry injects offset compensation charges into the comparator. During the conversion phase, the comparator operates with minimal loading to maintain high speed. This periodic switching between calibration and conversion modes allows the system to achieve precise offset mitigation without continuously burdening the comparator, thereby maintaining high productivity during the conversion phase
Data Source
AI summary
Analog-to-digital converter circuitry includes comparator circuitry, capacitor analog-to-digital converter circuitry (CDA), and successive approximation register (SAR) circuitry. The comparator circuitry includes a non-inverting input and an inverting input to selectively receive a differential voltage signal, and an output. The CDAC circuitry includes a first capacitor network having a first plurality of capacitors. A first capacitor of the first plurality of capacitors includes a first terminal connected to the non-inverting input and a second terminal selectively connected to a first voltage potential and a second voltage potential. The first voltage potential is greater than the second voltage potential. The SAR circuitry is connected to the output and the first capacitor network, and connects, during a first period, the second terminal of the first capacitor to the second voltage potential. The non-inverting input and the inverting input are connected to the differential voltage signal during the first period.