SAR ADC Offset Voltage Sequencing for Higher Resolution
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Solution Overview
Problem
Existing successive approximation analog-to-digital converters (ADCs) face challenges in achieving higher resolution without complex and unreliable methods, limiting their application in demanding scenarios.
Innovation Solution
Incorporating a digitally controlled offset voltage with a periodic pattern into the comparison stage of the successive approximation ADC, allowing for the generation of additional bits by sequentially processing multiple digital signals and summing them to achieve higher resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional successive approximation ADC methods are used, then the ADC can achieve normal resolution (e.g., 10-bit), but it cannot achieve higher resolution (e.g., 11-bit or 12-bit) without complex and unreliable methods
Solution Approach 1:
The patent segments the resolution enhancement process into multiple conversion cycles, where each cycle determines one additional bit. The N-bit ADC is divided into stages, with each stage processing a specific bit position through controlled offset voltage application, allowing systematic achievement of higher resolution without overwhelming complexity
Solution Approach 2:
The patent employs periodic action by applying offset voltages with specific periodic patterns during conversion cycles. The offset voltage follows a defined sequence (e.g., +Voffset, -Voffset, +Voffset, -Voffset) across multiple cycles, enabling systematic extraction of additional bit information through rhythmic, controlled variations that simplify the complexity of high-resolution conversion
2Reliability
If conventional successive approximation ADC methods are used, then the conversion process is straightforward, but it cannot reliably achieve higher resolution in demanding applications
Solution Approach 1:
The patent implements feedback mechanisms where the digital output from each conversion cycle is fed back to control the offset voltage application in subsequent cycles. The successive approximation logic uses previous conversion results to determine the next comparison point, creating a closed-loop system that reliably extracts each additional bit through feedback-driven decision making
Solution Approach 2:
The patent applies preliminary action by pre-defining the offset voltage patterns and conversion sequences before the actual high-resolution conversion begins. The system prepares the conversion pathway by establishing the offset voltage schedule and comparison sequence in advance, ensuring reliable execution of the complex multi-cycle conversion process without real-time decision complexity
3Measurement precision
If the ADC processes more conversion cycles to generate additional bits, then the resolution increases, but the conversion time increases
Solution Approach 1:
The patent maintains continuity of useful action by overlapping the determination of different bit positions across conversion cycles. While one bit is being determined in the comparator, other bits are being processed through the successive approximation logic in parallel, ensuring that the conversion process continues productively throughout without idle periods, thus minimizing time loss while achieving higher resolution
Data Source
AI summary
An apparatus includes a plurality of binary weighted capacitors coupled between a first input terminal of a comparator and a plurality of signal buses, wherein the plurality of binary weighted capacitors has a binary weight increasing by two times from a first capacitor to an (N−K)th capacitor, and a constant binary weight from the (N−K)th capacitor to a (N−K−2+2(K+1))th capacitor, an offset voltage generator configured to generate a digitally controlled offset voltage having 2(K+1) steps fed into a second input terminal of the comparator, and a successive approximation logic block configured to receive an output signal of the comparator, and generate an N-bit control signal for controlling the plurality of binary weighted capacitors.