SAR ADC Comparator Offset Detection via Top-Plate Swapping
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Solution Overview
Problem
High-speed analog-to-digital converters (ADCs) with moderate resolution and gigahertz sampling rates, particularly those using time interleaving structures, face performance degradation due to offset mismatch, gain mismatch, and timing skew, necessitating a more effective technique for detecting comparator offset.
Innovation Solution
A successive approximation register (SAR) ADC with a switch circuit, comparator, and calibration circuit that performs a 'top-plate swapping' operation to generate swapped analog signals, allowing for the detection of comparator offset by comparing intermediate and swapped signals to determine a calibration bit value and correct for offset.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If time interleaving structure is adopted to achieve high sampling rate, then sampling speed is improved, but offset mismatch and gain mismatch occur causing performance degradation
Solution Approach 1:
The patent performs offset detection and calibration before the actual conversion process. The switch circuit swaps the connections of the first and second intermediate analog signals to the comparator inputs, allowing offset detection to be performed in advance. This preliminary calibration action eliminates offset mismatch effects before they degrade the performance of high-speed time-interleaved ADC operation.
Solution Approach 2:
The patent changes the connection parameters of the comparator by using the switch circuit to swap which intermediate analog signal connects to which comparator input. By changing the signal routing parameters and performing comparisons with swapped connections, the system can detect and correct offset mismatch, thereby maintaining performance accuracy at high sampling rates.
2Measurement precision
If offset detection and calibration circuits are added to correct comparator offset, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The switch circuit performs multiple functions: it enables both normal signal routing during conversion and swapped signal routing during offset detection. The same comparator is used for both normal conversion and offset detection by changing its input connections. This multi-functionality improves measurement precision without proportionally increasing device complexity.
Solution Approach 2:
The system uses its own existing components (comparator, switch circuit, intermediate analog signals) to perform offset detection and calibration. The calibration process is self-contained within the existing ADC architecture, eliminating the need for external calibration equipment or separate dedicated calibration circuits, thereby improving precision while limiting complexity growth.
3Reliability
If additional channels or complex circuits are used to detect offset mismatch, then reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent extracts the offset detection function from separate additional channels or complex external circuits and integrates it into the existing ADC structure. By taking out the essential offset detection capability and implementing it using the existing comparator and switch circuit, the system improves reliability while avoiding the manufacturing costs associated with additional dedicated channels or complex external calibration equipment.
Data Source
AI summary
A successive approximation register (SAR) analog to digital converter (ADC) and a method of detecting an offset of a comparator are introduced. The SAR ADC includes a switch circuit, a comparator and a calibration circuit. The switch circuit is configured to perform a swapping operation on a first intermediate analog signal and a second intermediate analog signal to generate a first swapped analog signal and a second swapped analog signal. The comparator is coupled to the switching circuit and is configured to compare the first intermediate analog signal and the second intermediate analog signal before the swapping operation to generate a least-significant-bit value. The comparator is further configured to compare the first swapped analog signal and the second swapped analog signal after the swapping operation to generate a calibration bit value. The calibration circuit is configured to determine whether the comparator has an offset according to the least-significant-bit value and the calibration bit value.