SAR ADC With Shared Input Stage and Parallel Comparators
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional successive-approximation register (SAR) based Analog-to-Digital Converters (ADCs) face limitations in speed and complexity due to the use of a single comparator, which results in increased power consumption and noise, and requires complex logic to control the Digital to Analog Converter (DAC) and sample and hold circuitry.
Innovation Solution
The proposed solution involves a SAR based ADC with multiple parallel comparison and latch circuitries and a common trans-conductance input stage, where each circuitry acts as a separate comparator, reducing reset delays and logical complexity, and using a common input stage to load the DAC, thereby eliminating the need for complex SAR logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single comparator is used in conventional SAR ADC, then the device complexity is reduced, but the conversion speed decreases and power consumption increases
Solution Approach 1:
The patent divides the single comparator function into multiple parallel comparators (first comparator, second comparator, third comparator, fourth comparator), each handling specific bit comparisons simultaneously. This segmentation enables parallel processing of multiple bits, increasing conversion speed while the segmented architecture actually reduces the control logic complexity compared to sequential single-comparator approaches.
Solution Approach 2:
The patent transitions from a single-comparator sequential approach to a multi-comparator parallel architecture, adding the dimension of parallelism. Multiple comparators operate simultaneously on different bits, converting the time-sequential process into a spatially-parallel process, thereby achieving faster conversion without proportionally increasing control complexity.
2Speed
If multiple parallel comparators are used, then the conversion speed increases, but the power consumption and noise increase
Solution Approach 1:
The patent merges the input stages of multiple comparators into a shared common input stage that receives the analog input signal and DAC output simultaneously. This merging allows multiple comparators to operate in parallel for fast conversion while sharing resource infrastructure, thereby reducing the total power consumption and noise compared to having completely independent comparator circuits.
3Measurement precision
If a single comparator is used, then the power consumption is reduced, but the conversion speed and precision are limited
Solution Approach 1:
The patent segments the comparison function across four parallel comparators, each dedicated to specific bit comparisons (MSB, next bit, and two LSB comparisons). This segmentation achieves high conversion precision by simultaneously evaluating multiple bits, while the fixed parallel architecture reduces the complexity of control logic compared to sequential single-comparator methods that require complex state management.
4Speed
If multiple parallel comparators are used with separate input stages, then the conversion speed increases, but the loading on DAC and sample and hold circuitry increases
Solution Approach 1:
The patent merges all comparator input stages into a single common input stage that interfaces with the DAC and sample and hold circuitry. This consolidation allows multiple comparators to share the same input signal source, thereby maintaining fast parallel conversion speed while significantly reducing the loading burden on the DAC and sample and hold circuitry compared to having separate input stages for each comparator.
Data Source
AI summary
An Analog to Digital (ADC) is provided, where the ADC may include a sample and hold circuitry to sample an analog input signal, and a summation block to iteratively generate a subtraction signal. The subtraction signal may be based on a difference between the analog input signal and a feedback signal. The ADC may further include a common input stage to receive the subtraction signal, and a plurality of comparison and latch circuitries arranged in parallel, where individual ones of the plurality of parallel comparison and latch circuitries may sequentially receive an output of the common input stage.