SAR ADC Partial-Bit Conversion for Faster Low-Power Sampling
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Solution Overview
Problem
Conventional SAR ADCs have low conversion rates and high current consumption, particularly when performing multiple conversions, due to the need for a fixed number of clock cycles per bit determination, which complicates the process and increases power usage.
Innovation Solution
Implementing a partial mode in SAR ADC operations where the determination of certain bits is skipped based on previous conversion data, allowing for a reduced number of clock cycles in subsequent conversions, thereby improving conversion rate and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional SAR ADC performs fixed number of clock cycles for each bit determination, then conversion accuracy is maintained, but conversion rate is low and power consumption is high
Solution Approach 1:
The patent applies partial action by performing bit determination only when necessary. Instead of executing a fixed number of clock cycles for every conversion, the system dynamically determines the number of bits to convert based on comparison with previous results. When consecutive analog inputs are similar, fewer bits are determined (partial conversion), reducing clock cycles and power consumption while maintaining sufficient accuracy for the application.
Solution Approach 2:
The patent implements dynamics by making the conversion process adaptive rather than static. The algorithm dynamically adjusts the number of clock cycles based on real-time comparison between current and previous conversion results. This dynamic adaptation allows the system to optimize performance for each conversion operation, switching between full precision and reduced precision modes as needed.
2Measurement precision
If conventional SAR ADC performs full bit determination for every conversion, then measurement precision is maintained, but power consumption increases
Solution Approach 1:
The system performs partial bit determination based on the actual precision needed. When the analog input changes minimally between conversions, the system determines only a subset of bits rather than all N bits, reducing power consumption. The precision is dynamically adjusted to match the actual signal variation, avoiding unnecessary computational energy expenditure.
Solution Approach 2:
The patent changes the parameter of conversion precision dynamically. Instead of maintaining fixed N-bit precision for all conversions, the system adjusts the number of determined bits as a variable parameter. This parameter change is driven by comparing previous conversion results, allowing the system to operate at lower precision (and lower power) when high precision is not required.
3Productivity
If SAR ADC uses adaptive bit determination based on previous conversion data, then conversion rate improves, but device complexity increases
Solution Approach 1:
The patent implements feedback by comparing the current conversion result with the previous conversion result. This feedback mechanism determines whether to perform full bit determination or partial bit determination. The comparison outcome feeds back into the control logic, which then adjusts the conversion process accordingly, creating a closed-loop adaptive system that optimizes conversion rate based on actual signal characteristics.
Solution Approach 2:
The conversion system serves itself by automatically adjusting its own operation mode based on its output data. The system uses its own previous conversion results to determine the appropriate level of precision for the current conversion, eliminating the need for external control or complex preprocessing. This self-service approach simplifies the overall system architecture while maintaining adaptive performance.
Data Source
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AI summary
A successive approximation register (SAR) analog-to-digital converter (ADC) may be used to generate a first digital data of N-bit and a second digital data of N-bit for an analog data. When the second digital data and the first digital data include a first sequence of most significant bits (MSBs) having same values, a third digital data of N-bit may be generated for the analog data using the SAR ADC in a partial mode. In the partial mode, the SAR ADC is configured to skip determining a second sequence of MSBs of the third digital data, and only determine remaining bits of the third digital data. When the second digital data and the first digital data do not include the first sequence of MSBs having same values, the SAR ADC operates in a full mode to determine every bit of the N-bit third digital data.