SAR ADC Comparator Offset Tracking via Partial DAC Conversion
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Solution Overview
Problem
Successive-approximation-register analog-to-digital converters (SAR ADCs) face challenges due to inherent comparator offsets that vary with time, temperature, and voltage, requiring efficient offset cancellation systems that do not consume additional power and maintain zero power tracking while improving signal-to-noise ratio (SNR).
Innovation Solution
The system employs a capacitive digital-to-analog converter (DAC) with a control module that performs full and partial conversions to determine and compensate for comparator offsets, using multiple capacitive DACs and control modules to generate signals for offset calculation and future conversion control, allowing for zero power tracking and enhanced SNR without an auto-zero phase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional offset cancellation methods are used, then comparator offset can be compensated, but additional power is consumed and auto-zero phase is required
Solution Approach 1:
The patent performs a partial conversion with only M bits (where M < N) instead of a full N-bit conversion to determine comparator offset. This partial action reduces the time and power required for offset cancellation while still achieving effective offset compensation. The reduced conversion length directly addresses the power consumption issue by minimizing the duration of offset determination operations.
Solution Approach 2:
The patent determines comparator offset during the normal conversion process itself, rather than requiring a separate preliminary auto-zero phase. The offset determination is integrated into the conversion workflow, eliminating the need for additional preparatory steps that would consume extra power and time.
2Measurement precision
If full N-bit conversion is performed to determine offset, then accurate offset cancellation is achieved, but conversion time increases
Solution Approach 1:
The patent performs a partial conversion with M bits (M < N) to determine comparator offset, rather than completing a full N-bit conversion. This partial action achieves sufficient offset determination accuracy for effective compensation while significantly reducing the time required. The reduced bit depth for offset determination directly addresses the time loss issue.
3Reliability
If comparator offset varies with time and temperature, then offset compensation becomes less reliable, but system complexity increases with additional compensation circuits
Solution Approach 1:
The patent implements a feedback mechanism where the determined comparator offset is stored and used to adjust subsequent conversion operations. The SAR control module applies the determined offset to compensate for variations in real-time, improving reliability without requiring complex additional compensation circuits. The feedback loop continuously maintains accurate offset compensation despite environmental variations.
Solution Approach 2:
The system uses its own conversion process to determine and compensate for comparator offset, rather than requiring external or separate compensation circuits. The SAR ADC performs self-diagnosis and self-correction by utilizing its existing components (capacitive DAC, comparator, control module) to identify and compensate for offset errors, thereby improving reliability without increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster comparator offset cancellation, maintains zero power tracking, and improves the signal-to-noise ratio by approximately 3 decibels, effectively addressing the variability of comparator offsets in SAR ADCs.
Implementation Method 1
The first capacitive DAC has a size less than a second DAC of the SAR ADC, and each of the first and second capacitive DACs receives a value and a reference value
Data Source
AI summary
A system for a successive-approximation-register analog-to-digital-converter (SAR ADC) includes a first capacitive digital-to-analog converter (DAC), first and second conversion control modules, and an SAR control module. The first capacitive DAC has a size less than a second DAC of the SAR ADC. The first conversion control module generates first and second signals for a comparator of the SAR ADC based on outputs of the first and second capacitive DACs and an analog input signal. The second conversion control module generates third and fourth signals for the SAR control module of the SAR ADC based on outputs of the comparator. The SAR control is configured to (i) control the first and second conversion control modules during a full conversion and a following partial conversion, (ii) determine an offset of the comparator, and (iii) control the SAR ADC based on the determined comparator offset.