SAR ADC CDAC Reconfiguration for Lower Reference Charge Variation
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Solution Overview
Problem
Successive approximation register (SAR) analog-to-digital converters (ADCs) face challenges in minimizing input signal-dependent charge drawn from a reference voltage circuit, leading to non-linearity and increased power consumption, especially when using capacitive digital-to-analog converters (CDACs) with high resolution.
Innovation Solution
The SAR ADC reconfigures the CDAC switches after conversion to reduce input signal-dependent charge by reverting switches to their pre-bit-decision state, thereby reducing the output impedance of the reference voltage circuit and power consumption while improving linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If CDAC switches are maintained in post-conversion state, then conversion speed is improved, but input signal dependent charge drawn from reference voltage circuit increases causing non-linearity
Solution Approach 1:
The patent applies periodic action by implementing a two-phase operational cycle: during the conversion phase, switches are configured for high-speed bit determination, and after conversion completes, switches are reconfigured to a second state that minimizes signal-dependent charge. This periodic switching between operational modes resolves the contradiction by ensuring linearity is restored after the speed-critical conversion phase.
Solution Approach 2:
The patent employs dynamics by making the CDAC switch configuration adaptive and time-varying. The switch states are dynamically adjusted based on the conversion status: during active conversion, switches are in a first configuration enabling rapid successive approximation; after conversion, switches transition to a second configuration that eliminates signal-dependent charge effects. This dynamic reconfiguration allows the system to optimize for speed during conversion and for linearity after conversion.
2Measurement precision
If CDAC switches are reconfigured after conversion, then input signal dependent charge is reduced improving linearity, but additional switching operations increase power consumption
Solution Approach 1:
The patent extracts the linearity-critical function from the continuous operational state by isolating it to a post-conversion phase. The switch reconfiguration extracts the signal-dependent charge component from the reference voltage circuit after conversion completes, separating the speed function (during conversion) from the linearity function (after conversion). This extraction allows linearity improvement without requiring continuous energy expenditure.
Solution Approach 2:
The patent treats the post-conversion switch configuration as a temporary, low-cost state that exists only briefly after conversion completes. The reconfiguration is a short-lived action that eliminates signal-dependent charge for the minimal duration needed to prepare for the next conversion cycle, rather than maintaining a complex continuous correction mechanism that would consume more power.
3Measurement precision
If high resolution CDAC is used, then ADC resolution is improved, but variation in charge drawn from reference voltage circuit increases
Solution Approach 1:
The patent converts the harmful signal-dependent charge variation into a beneficial state by deliberately configuring switches in a second state after conversion. The same switch mechanism that creates charge variation during conversion is repurposed after conversion to eliminate that variation. By inverting the switch configuration, the patent transforms the source of harm into the solution, achieving linearity improvement without sacrificing the high-resolution capability during the conversion phase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the variation in charge drawn from the reference voltage circuit by a factor of about 16, allowing for relaxed output impedance and decreased power consumption, while maintaining high resolution and linearity in the ADC output.
Implementation Method 1
reconfiguring the capacitive digital-to-analog converter (CDAC) after conversion is complete
Data Source
AI summary
An analog-to-digital converter (ADC) includes a capacitive digital-to-analog converter (CDAC), a comparator coupled to the CDAC, and a successive approximation register (SAR) control circuit coupled to the CDAC and the comparator. The SAR control circuit is configured to successively select bits of a digital output value. The SAR control circuit is also configured to, after selection of the bits of the digital output value: maintain a state of first switches of the CDAC applied to select a most significant bit of the digital output value, and revert second switches of the CDAC applied to select bits of the digital output value having significance lower than the most significant bit to a state of the second switches prior to selection of the most significant bit.