SAR ADC Pre-Distortion for Comparator Capacitance Nonlinearity
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Solution Overview
Problem
High-resolution SAR ADCs face performance degradation due to comparator input parasitic capacitance non-linearity, which cannot be readily corrected by calibration, and existing solutions are either impractical or inefficient in terms of power dissipation and area reduction.
Innovation Solution
A pre-distortion technique is introduced, where the sampled input signal is pre-distorted using the comparator input capacitance before bit-cycling, effectively compensating for the non-linear capacitance variation by scaling the DAC steps and reducing the impact of comparator input capacitance during the conversion process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If calibration is used to correct DAC capacitor mismatch, then manufacturing precision is improved, but device complexity increases due to additional calibration circuitry
Solution Approach 1:
The patent extracts the comparator from the main conversion path and uses it in a separate calibration mode. During calibration, the comparator is configured to measure capacitor mismatches without affecting the normal ADC operation, thereby separating the calibration function from the conversion function and reducing overall device complexity.
Solution Approach 2:
The patent implements calibration as a periodic operation that occurs at specific intervals or under specific conditions rather than continuously. The comparator is activated in calibration mode periodically to measure and correct capacitor mismatches, while the ADC operates in normal conversion mode during other periods, reducing the active complexity at any given time.
2Manufacturing precision
If physical area of DAC elements is increased to improve matching, then manufacturing precision is improved, but area consumption increases
Solution Approach 1:
The patent replaces the physical approach of increasing capacitor area for better matching with an electrical measurement and correction approach. Instead of making capacitors physically larger to reduce mismatch, the patent uses the comparator to measure the actual mismatch values and applies digital correction, substituting physical dimension changes with electrical measurement and processing.
3Measurement precision
If comparator input capacitance is reduced to improve linearity, then measurement precision is improved, but reliability deteriorates due to increased sensitivity to parasitics
Solution Approach 1:
The patent creates a copy of the capacitor array specifically for calibration purposes. This calibration capacitor array is identical to the main DAC capacitor array, allowing the comparator to measure mismatch characteristics without affecting the main conversion path. The copying approach allows separate optimization of the calibration path while maintaining the integrity of the main conversion path.
Solution Approach 2:
The patent introduces a calibration mode as an intermediary operation between the input signal and the comparator. During calibration, the system switches to a special configuration where test signals are applied and comparator responses are measured to characterize mismatches, acting as an intermediary measurement step that separates the characterization function from the conversion function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This technique significantly reduces non-linearity, improving the ADC's signal-to-noise-plus-distortion ratio by over 3.5 bits, as shown in simulation results, and achieves efficient power dissipation and area reduction by minimizing the impact of comparator capacitance variations.
Implementation Method 1
the comparator input capacitance is input-signal dependent, and hence introduces non-linearity to the transfer characteristics of the ADC
Implementation Method 2
effectively compensating for the non-linear capacitance variation by scaling the DAC steps
Data Source
AI summary
Successive-approximation-register (SAR) analog-to-digital conversion technique continues to be one of the most popular analog-to-digital conversion techniques, due to their versatility, which allows providing high resolution output or high conversion rates. In addition, SAR analog-to-digital converters (ADC) have a modest circuit complexity that results in low-power dissipation. A SAR ADC is, typically, composed of a single comparator, a bank of capacitors and switches, in addition to, a control digital logic. However, the comparator input capacitance is input-signal dependent, and hence introduces non-linearity to the transfer characteristics of the ADC. A simple technique is devised to significantly reduce this non-linearity, by pre-distorting the sampled-and-held input signal using the same comparator input capacitance.