SAR ADC Preload Offset for Bit-Boundary Conversion Accuracy
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Solution Overview
Problem
Successive approximation register (SAR) analog-to-digital converters (ADCs) face errors when the most significant bit (MSB) is preloaded based on previous digital outputs, especially when the input signal is near the bit boundary, leading to inefficiencies and increased power consumption.
Innovation Solution
The method involves comparing a previous digital output to a range defined by its first M bits and applying an offset if it's near the boundary, allowing the SAR ADC to preload bits that center the previous digital output within a predefined range, reducing the likelihood of errors and improving conversion efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the MSB is preloaded based on the previous digital output, then power consumption is reduced and conversion speed is improved, but errors occur when the input signal is near the bit boundary
Solution Approach 1:
The patent preloads the MSB of the DAC based on the previous digital output before the actual conversion begins. This preliminary action allows the converter to skip bit trials for the MSB when the input signal is slow-moving, thereby reducing power consumption and increasing conversion speed while maintaining accuracy through subsequent bit trials
Solution Approach 2:
The patent uses the previous digital output as feedback to determine the preload value for the current conversion. By comparing the previous output with the current input signal, the system can intelligently decide whether to apply the preload and what value to use, preventing errors near bit boundaries while maintaining the benefits of preloading
2Loss of time
If the MSB is preloaded to speed up the process, then fewer bit trials are needed, but errors occur when the input signal moves towards the bit boundary
Solution Approach 1:
The MSB is preloaded in advance based on the previous digital output, eliminating the need for bit trials on the MSB when conditions are favorable. This preliminary action reduces conversion time by one clock cycle while maintaining accuracy through the conditional nature of the preload and subsequent verification bit trials
Solution Approach 2:
The patent dynamically changes the operating parameters of the DAC by adjusting the preload value based on the previous digital output. When the previous output indicates the input is near a bit boundary, the preload is adjusted or not applied, thereby adapting the conversion process to maintain accuracy while minimizing conversion time
Data Source
AI summary
A method of performing analog-to-digital conversion using a successive approximation (SAR) analog-to-digital converter (ADC). A previous digital output is compared to a range based on the first M bits of the previous digital output. If the previous digital output is within that range, a digital-to-analog converter (DAC) of the SAR ADC is preloaded with the first M bits of the previous digital output, prior to commencing bit trials. If the previous digital output is outside of that range, an offset is applied to the first M bits of the previous digital output and the DAC is preloaded based on the M bits and the offset, prior to performing bit trials. This method reduces the possibility of the next input being outside of a further range defined by the preload.