Capacitor-Array SAR ADC for Low-Voltage Rail-to-Rail Input
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Solution Overview
Problem
Conventional analog-to-digital converters (ADCs) face challenges in operating at low supply voltages with low power consumption and achieving a rail-rail input range, which is essential for battery-operated medical devices that require monitoring weak biomedical signals.
Innovation Solution
A modified successive approximation ADC design that uses a binary-weighted capacitor array with CMOS switches connected in series, a comparator with a reference voltage of VDD/2, and a successive approximation register to control switches, eliminating the need for an extra capacitor and reducing power consumption by integrating a pseudo sample-and-hold function within the ADC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If conventional successive approximation ADC based on charge redistribution is used, then low power operation is achieved, but the ADC cannot operate at low supply voltage due to high impedance of CMOS switches for signals near half of VDD
Solution Approach 1:
The capacitor array is divided into two separate capacitor arrays: a first capacitor array connected to the input signal and a second capacitor array connected to the reference voltage. This segmentation allows each array to operate within optimized voltage ranges, enabling low-voltage operation while maintaining low power consumption through the conventional charge redistribution mechanism.
Solution Approach 2:
A differential amplifier is introduced as an intermediary component between the capacitor arrays and the comparator. This differential amplifier buffers the signals, allowing the ADC to operate at low supply voltages by translating the voltage levels appropriately, thus resolving the impedance issue of CMOS switches at low voltages while preserving the low-power charge redistribution operation.
2Device complexity
If input signal is directly fed to comparator without scaling, then circuit complexity is reduced, but input range is limited to common-mode input range or half of VDD
Solution Approach 1:
The first capacitor array serves multiple functions: it acts as both the sampling capacitor for the input signal and part of the DAC structure during conversion. This multi-functionality enables rail-rail input range capability without adding separate scaling circuits, thus maintaining low complexity while achieving full input voltage range from GND to VDD.
Solution Approach 2:
The ADC architecture transitions from a single-ended structure to a differential structure by using two capacitor arrays and a differential amplifier. This dimensional change in the signal processing approach enables the circuit to handle the full rail-to-rail input voltage range while keeping the comparator operation within its common-mode range, effectively expanding adaptability without proportionally increasing complexity.
3Adaptability or versatility
If extra capacitor is added to achieve rail-rail input range, then input range is expanded, but manufacturing cost increases
Solution Approach 1:
The sampling function and the DAC function are merged into a unified capacitor array structure. The first capacitor array performs both sampling of the input signal and serves as part of the digital-to-analog conversion mechanism. This merging eliminates the need for separate extra capacitors that would be required for signal scaling, thereby achieving rail-rail input range without increasing manufacturing cost.
Solution Approach 2:
The capacitor arrays are designed to automatically perform signal scaling and level translation through their inherent charge redistribution mechanism during the conversion process. The system uses its own existing components (the capacitor arrays and differential amplifier) to achieve rail-rail input capability without requiring external or additional capacitors, thus avoiding increased manufacturing cost while expanding input range.
4Ease of operation
If separate sample-and-hold circuit is used before ADC, then sampling function is provided, but chip area and power consumption increase
Solution Approach 1:
The sample-and-hold function is merged with the first capacitor array and the input switch. During the sampling phase, the input switch connects the input signal to the first capacitor array, which holds the sampled voltage. This integration eliminates the need for a separate sample-and-hold circuit, reducing chip area while maintaining the sampling capability through the existing ADC components.
Solution Approach 2:
The first capacitor array serves multiple functions: it acts as the sampling capacitor during the sampling phase, as part of the DAC during the conversion phase, and provides the hold function by maintaining the sampled voltage. This multi-functionality achieves the sampling operation without requiring a dedicated sample-and-hold circuit, thereby reducing chip area and power consumption while maintaining ease of operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables low-voltage, low-power ADC operation with a rail-rail input range, reducing power consumption and chip area, and achieving accurate A/D conversion with minimal error, suitable for battery-operated medical devices like EEG and ECG devices.
Implementation Method 1
Successive approximation ADC based on charge redistribution has been widely used in low power applications
Data Source
AI summary
An analog-to-digital converter (ADC) and a battery operated electronic device comprising the ADC. The ADC comprising an input switch; an array of binary-weighted capacitors, the array of capacitors receiving the input voltage signal via the input switch in an on state of the input switch; a plurality of switches, each switch connected in series with a respective one of the capacitors at an opposite side compared to the input switch, wherein a VDD signal is applied to each switch in one switching state and ground in another switching state; a comparator having as one input a voltage from the input switch side of the array of capacitors and as another input a voltage of VDD/2; and a switch control unit coupled to an output of the comparator for controlling the switches based on the output from the comparator.