SAR ADC Calibration Using Ramp Comparison for Accurate Conversion
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Solution Overview
Problem
The successive approximation system in analog-to-digital converters is susceptible to manufacturing errors that affect capacitance values, leading to inaccurate digital data due to incorrect bias voltage values.
Innovation Solution
An analog-to-digital converter design that combines a counter-ramp system with a successive approximation system, using a sample-and-hold circuit, a ramp waveform signal generation unit, and a control unit to generate bias voltages and compare them with a referential voltage, allowing for calibration data to be obtained and used to compensate for capacitance variations, ensuring accurate digital conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a successive approximation system is used to increase conversion speed, then productivity is improved, but manufacturing precision deteriorates due to capacitance value variations
Solution Approach 1:
The patent applies preliminary action by performing calibration measurements before actual conversion operations. The system pre-measures the actual capacitance values of all capacitors in the successive approximation register (SAR) using a ramp voltage generator and comparator, stores these measured values in memory, and uses them to correct conversion results. This preliminary characterization eliminates the need for precise manufacturing while maintaining high conversion speed.
Solution Approach 2:
The patent implements feedback by using the measured capacitance values to correct the conversion output. The system feeds back the actual capacitance characteristics into the conversion process through correction calculations, compensating for manufacturing variations. This feedback mechanism allows the system to achieve high precision despite capacitance value variations, while maintaining the high speed advantage of the successive approximation system.
2Measurement precision
If capacitance values vary due to manufacturing errors, then device complexity increases due to need for calibration, but measurement precision deteriorates without calibration
Solution Approach 1:
The patent applies self-service by enabling the ADC to calibrate itself automatically. The system includes a calibration mode where the SAR internally measures its own capacitor values using the ramp voltage generator and comparator, stores these values in on-chip memory, and uses them for correction during normal operation. This self-calibration approach eliminates the need for external calibration equipment or complex manual adjustment circuits, achieving high measurement precision with moderate device complexity.
3Reliability
If bias voltage values become incorrect due to capacitance variations, then reliability deteriorates, but use of energy increases with additional correction circuits
Solution Approach 1:
The patent merges the calibration function with the existing conversion circuitry. The ramp voltage generator, comparator, and SAR capacitors are used for both normal conversion operations and calibration measurements. The same control logic manages both conversion and calibration modes, and the correction calculation is integrated into the output generation process. This merging approach achieves high reliability through capacitance compensation without requiring separate correction circuits, thereby minimizing additional power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the achievement of accurate digital data in analog-to-digital conversion by compensating for capacitance variations, thereby improving the reliability of the successive approximation system.
Implementation Method 1
a ramp waveform signal generation unit that generates a ramp waveform signal based on the count signal
Implementation Method 2
a successive approximation capacitance group that has a predetermined number of capacitances having different capacitance values that successively increase by a factor of two, and outputs bias voltages having different levels by changing connection of the capacitances
Implementation Method 3
a comparison unit that compares a voltage not to be added serving as the other of the voltage held by the sample-and-hold circuit and the predetermined referential voltage and the addition voltage
Data Source
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AI summary
To obtain accurate digital data while using a successive approximation system when performing analog-to-digital conversion processing in a plurality of steps. There is provided an AD converter including a ramp waveform signal generation unit (14) that generates a ramp voltage based on a count signal from a counter (15), a signal conversion unit (13), and a control unit (18), in which the signal conversion unit (13) includes a sample-and-hold circuit that holds an input signal voltage, a successive approximation capacitance group (16) that outputs a plurality of bias voltages according to a connection combination of a predetermined number of capacitances having different capacitance values, and a comparison unit (17) that compares one of the ramp voltage and the bias voltage with the signal voltage, and the control unit (18) generates a digital signal of the signal voltage based on a comparison result by the comparison unit (17) of the bias voltage and the signal voltage and a comparison result by the comparison unit (17) of the ramp voltage and the signal voltage while acquiring data for calibration of the successive approximation capacitance group (16) based on the connection combination of the capacitances and the ramp voltage.