SAR ADC C-R Hybrid DAC Timing for Lower RDAC Power
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Solution Overview
Problem
Successive approximation register (SAR) analog-to-digital converters (ADCs) face challenges in reducing power consumption due to increased operating current, particularly in capacitor-resistor (C-R) hybrid digital-to-analog converter (DAC) structures, which are common in high-resolution applications.
Innovation Solution
The implementation of a SAR ADC with a C-R hybrid DAC circuit, a comparator, and a control logic circuit that uses a driving clock with a duty cycle greater than the system clock to extend the voltage settling period after switch changes, thereby reducing power consumption by minimizing current increase in the resistor digital-to-analog converter (RDAC) circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of the SAR ADC is increased using a C-R hybrid DAC structure, then the conversion precision is improved, but the operating current increases leading to higher power consumption
Solution Approach 1:
The DAC is segmented into two independent structures: a capacitor-based DAC (CDAC) for handling significant bits and a resistor-based DAC (RDAC) for handling fractional bits. This segmentation allows each structure to operate optimally for its specific bit range, reducing the overall current consumption while maintaining high-resolution conversion capability.
Solution Approach 2:
The patent dynamically controls the switching between different DAC structures based on the bit significance. The CDAC and RDAC are selectively activated depending on whether significant bits or fractional bits are being converted, optimizing power consumption by keeping only the necessary DAC structure active at any given time.
2Use of energy by moving object
If the voltage settling period is extended to reduce current increase in the RDAC circuit, then the power consumption is reduced, but the conversion time increases
Solution Approach 1:
The conversion process is segmented into two distinct phases: significant bit conversion using CDAC and fractional bit conversion using RDAC. Each phase has its own optimized settling time requirements, allowing the system to achieve accurate conversion without requiring the entire conversion process to accommodate the longer RDAC settling time.
Solution Approach 2:
The patent employs periodic clock signals with different duty cycles to control the switching between CDAC and RDAC operations. By using a driving clock with a duty cycle greater than 50%, the system allocates sufficient time for voltage settling during each conversion phase while maintaining an overall efficient conversion rhythm that minimizes total conversion time.
Data Source
AI summary
The present disclosure relates to an analog-to-digital converter that reduces power consumption by reducing an operating current and a semiconductor device having the same. The analog-to-digital converter includes a capacitor-resistor (C-R) hybrid digital-to-analog converter (DAC) circuit including a capacitor digital-to-analog converter (CDAC) circuit including a capacitor array, and a resistor digital-to-analog converter (RDAC) circuit including a resistor string, a comparator that compares an output voltage of the C-R hybrid DAC circuit with a common mode voltage and outputs a comparison result, and a control logic circuit that controls a switch operation of the C-R hybrid DAC circuit and the comparison operation of the comparator using a driving clock with a duty cycle greater than a duty cycle of the first clock based on a system clock, and determines each bit of digital data by receiving the comparison result of the comparator.