SAR ADC Comparator-Driven Read Clock for Faster Conversion
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Solution Overview
Problem
Existing SAR ADCs face a slowdown in conversion speed due to the need for a separate read clock that must be delayed to prevent metastability, which is influenced by input and environmental variations, leading to inefficiencies.
Innovation Solution
The SAR ADC uses the comparator's output as a clock to read the comparison result immediately after generation, eliminating the need for a separate read clock and allowing dynamic adjustment of the delay, thereby improving conversion speed and handling metastable states without resetting the comparator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate read clock is used to read the comparator output, then metastability can be prevented, but the conversion speed is reduced due to required delay
Solution Approach 1:
The patent combines the comparator clock and read clock functions into a single clock signal. The read clock is generated by delaying the comparator clock through a delay circuit, eliminating the need for a separate read clock and reducing the overall delay requirement while still preventing metastability.
Solution Approach 2:
The patent uses a dynamic delay circuit that adjusts the delay based on the operating conditions. The delay is dynamically optimized to be just sufficient to prevent metastability without the excessive fixed delay required in traditional designs, thereby improving conversion speed while maintaining reliability.
2Reliability
If the delay between comparator clock and read clock is increased to cover maximum d1, then reading reliability is ensured, but conversion speed is slowed down
Solution Approach 1:
The patent changes the delay parameter from a fixed large value to a dynamically adjusted value. The delay circuit optimizes the delay time based on actual operating conditions, using only the minimum necessary delay to ensure reliable reading, thus reducing the time loss without compromising reading reliability.
3Ease of operation
If a separate read clock independent of comparator clock is used, then reading can be controlled independently, but device complexity increases
Solution Approach 1:
The patent merges the independent clock control functionality into the comparator clock path by using a delay circuit derived from the same clock source. This eliminates the need for a completely separate read clock circuit while still providing the necessary independent timing control for reading the comparator output.
Data Source
AI summary
A SAR ADC and an electronic device are disclosed. The SAR ADC includes a read clock generation circuit, configured to connect to a first output terminal and a second output terminal of a dynamic comparator, and generate a read clock signal for reading a first or a second comparison result based on the first and the second comparison result received from the dynamic comparator. The invention reads the comparison result using the read clock signal generated by grabbing the output of the comparator, and can improve the overall analog-to-digital conversion speed of the SAR ADC. Further, the present invention can detect the occurrence of metastable state of the comparator by judging that the output of the comparator has no pulse, and read the comparison result based on the backup clock generated by the operating clock of the comparator.