SAR ADC Architecture Using a Reduced-Bit DAC

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Solution Overview

Problem

Conventional SAR ADC architectures require a DAC with the same resolution as the ADC, leading to high power consumption, large size, and manufacturing difficulties due to the need for good matching.

Innovation Solution

A SAR ADC configuration where the DAC has fewer bits of resolution than the ADC, utilizing a comparator and SAR logic to generate a digital output word with more bits than the DAC, by determining the MSB and subsequent bits through comparisons with a reference voltage, allowing for efficient digital representation of an analog input voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the DAC uses the same resolution as the SAR ADC, then the ADC achieves high measurement precision, but the power consumption increases significantly

Engineering Contradiction:
ImproveADC resolutionVSAvoidDAC power consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent segments the resolution function between the DAC and the SAR logic. The DAC is assigned a reduced resolution (N bits) while the SAR logic compensates by generating the remaining bits through iterative comparison operations. This segmentation allows the power-hungry DAC to operate at lower resolution while the overall system maintains full N+M bit precision through the combined action of DAC and SAR logic.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If the DAC uses the same resolution as the SAR ADC, then the ADC achieves high measurement precision, but the device size becomes large

Engineering Contradiction:
ImproveADC resolutionVSAvoidDAC size
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent segments the resolution function between the DAC and the SAR logic. The DAC is assigned a reduced resolution (N bits) while the SAR logic compensates by generating the remaining bits through iterative comparison operations. This segmentation allows the power-hungry DAC to operate at lower resolution while the overall system maintains full N+M bit precision through the combined action of DAC and SAR logic.

Inventive Principle:
Principle #1Segmentation

3Measurement precision

If the DAC uses the same resolution as the SAR ADC, then the ADC achieves high measurement precision, but the manufacturing complexity increases due to matching requirements

Engineering Contradiction:
ImproveADC resolutionVSAvoidDAC manufacturing
Core Design Contradiction:
Measurement precisionVSEase of manufacture

Solution Approach 1:

The patent segments the resolution function between the DAC and the SAR logic. The DAC is assigned a reduced resolution (N bits) while the SAR logic compensates by generating the remaining bits through iterative comparison operations. This segmentation allows the power-hungry DAC to operate at lower resolution while the overall system maintains full N+M bit precision through the combined action of DAC and SAR logic.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The SAR logic acts as an intermediary that bridges the gap between the reduced-resolution DAC and the full-resolution ADC output. Through iterative comparison and bit-generation operations, the SAR logic translates the DAC's limited precision into the full precision required by the ADC, eliminating the need for the DAC to inherently support the full resolution.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Use of energy by moving object

If the DAC uses fewer bits than the SAR ADC, then power consumption and device size are reduced, but the DAC alone cannot provide sufficient resolution

Engineering Contradiction:
ImproveDAC power consumptionVSAvoidDAC resolution
Core Design Contradiction:
Use of energy by moving objectVSMeasurement precision

Solution Approach 1:

The patent merges the functionality of the reduced-resolution DAC with the iterative SAR logic to achieve full ADC resolution. The DAC provides the initial voltage based on its N-bit digital input, and the SAR logic merges this with additional bit-generation through comparison operations to produce the final N+M bit digital output, combining both components' contributions to achieve the desired precision.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10735017B2Efficient successive approximation register analog to digital converter
Publication Date: 2020.08.04 SHENZHEN GOODIX TECH CO LTD
  • US10735017B2 patent drawing
  • US10735017B2 patent drawing
  • US10735017B2 patent drawing

AI summary

A successive approximation register (SAR) analog to digital converter (ADC) is disclosed. The SAR ADC includes: a DAC, configured to receive an analog input voltage and a digital input word, and to generate a first voltage. The SAR ADC also includes a comparator, configured to generate a second voltage based on the first voltage and a reference voltage. The second voltage has a value corresponding with a sign of the difference between the first voltage and the reference voltage. The SAR ADC also includes an SAR logic circuit configured to receive the second voltage from the comparator, and to generate the digital input word for the DAC. The SAR logic is further configured to generate a digital output word representing the value of the analog input voltage, where the digital output word of the SAR logic has a greater number of bits than the digital input word of the DAC.