SAR ADC Redundant DAC Correction for Faster Precise Conversion
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Solution Overview
Problem
Successive-approximation analog-to-digital converters face increased processing time due to repeated sampling and successive-approximation processes, which can lead to longer conversion times and reduced precision.
Innovation Solution
Incorporating a redundant DAC and a correction circuit that corrects errors in the upper bit using a redundant bit and averages conversion values to reduce processing time, while omitting the primary successive approximation for upper bits and focusing on secondary successive approximation for lower bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple sampling and successive-approximation processes are performed to improve AD conversion precision, then measurement precision is improved, but processing time increases
Solution Approach 1:
The patent segments the successive approximation process into two distinct phases: a first successive approximation process for upper bits and a second successive approximation process for lower bits. This segmentation allows different processing strategies to be applied to different bit ranges, optimizing both precision and speed. The upper bits are determined first with coarser resolution, then the lower bits are refined separately, avoiding the need for multiple complete conversion cycles.
Solution Approach 2:
The patent performs preliminary determination of upper bits through the first successive approximation process before undertaking the second successive approximation process for lower bits. This preliminary action establishes a foundation that guides the subsequent refinement process, allowing the system to achieve high precision without repeating the entire conversion process multiple times.
2Measurement precision
If multiple AD conversion processes are performed and averaged to reduce noise effect, then measurement precision is improved, but productivity decreases
Solution Approach 1:
The patent divides the conversion process into segmented stages where upper bits are determined in a first stage and lower bits are determined in a second stage. This segmentation eliminates the need to perform multiple complete conversion cycles and average the results, as the two-stage process inherently provides noise immunity while maintaining high conversion speed.
Solution Approach 2:
The patent extracts the noise-sensitive lower bit determination from the upper bit determination process. By separating the determination of upper bits (less sensitive to noise) from lower bits (more sensitive to noise), the system can apply appropriate processing to each, achieving high precision without requiring multiple complete conversion cycles.
3Measurement precision
If a redundant DAC and correction circuit are added to correct upper bit errors, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent creates a copy of the DAC structure (redundant DAC) specifically for verifying and correcting upper bit determinations. This copying approach allows the system to cross-validate upper bit values without requiring complex error detection and correction logic, as the redundant DAC provides a parallel verification path that simplifies the overall correction mechanism.
Solution Approach 2:
The patent implements feedback mechanisms where the correction circuit uses comparison results from the redundant DAC to adjust and correct upper bit determinations. This feedback loop ensures high accuracy by continuously verifying and correcting upper bit values based on the redundant measurement path, maintaining precision without requiring overly complex forward-looking control logic.
Data Source
AI summary
A semiconductor device includes an analog-to-digital converter configured to perform a process of sampling an analog input signal and a successive-approximation process, execute an AD conversion process, and output a digital output signal. The AD converter includes an upper DAC, a redundant DAC, a lower DAC, a comparator configured to compare a comparative reference voltage and output voltages of the upper DAC, the redundant DAC and the lower DAC, a control circuit configured to control successive approximations by the upper DAC, the redundant DAC and the lower DAC based on the comparison result of the comparator, and generate a digital output signal, and a correction circuit. The correction circuit includes an error correction circuit configured to correct an error of the upper bit with the redundant bit, and an averaging circuit configured to calculate an average value of conversion values of a plurality of the lower bits supplied multiple times.