SAR ADC Data Register With High-Speed Flip-Flops and Fewer Transistors
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Solution Overview
Problem
Conventional SAR ADCs require a large number of transistors and operate slowly due to the use of conventional D flip-flops in their data register units, which limits their speed and efficiency.
Innovation Solution
A high-speed flip-flop circuit with a simple structure is introduced, comprising a PMOS transistor, an NMOS transistor, an inverter, and a logic gate, which reduces the number of transistors required and enhances operation speed by combining bit pulses to achieve capacitor switching based on comparison results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional D flip-flops are used in the data register unit, then reliability is maintained, but operation speed is slow and transistor count is high
Solution Approach 1:
The data register unit is segmented into multiple high-speed flip-flop circuits, each handling specific bit positions. This segmentation allows parallel operation and reduces the critical path delay, thereby increasing operation speed while using fewer transistors per functional unit compared to conventional D flip-flops
Solution Approach 2:
The patent uses simplified high-speed flip-flop circuit designs that replicate essential flip-flop functionality with fewer transistors. By copying this optimized circuit structure across multiple bit positions in the data register, the system achieves high-speed operation with reduced overall transistor count
2Device complexity
If conventional D flip-flops are used in the data register unit, then reliable operation is achieved, but the structure becomes complex and power consumption increases
Solution Approach 1:
The patent extracts and removes unnecessary circuit components from the conventional D flip-flop structure, keeping only the essential elements needed for high-speed operation. This extraction simplifies the structure and reduces transistor count while maintaining the core functionality and reliability of the flip-flop operation
Solution Approach 2:
The patent changes key parameters of the flip-flop circuit, such as transistor sizing, gate lengths, and doping concentrations, to optimize for high-speed operation. These parameter changes enable the simplified structure to achieve reliability comparable to or better than conventional designs while using fewer transistors
3Reliability
If the data register uses more transistors for reliable operation, then reliability improves, but operation speed decreases and area increases
Solution Approach 1:
The patent implements dynamic circuit techniques in the high-speed flip-flop design, such as dynamic logic gates and clocked switches, which enable faster switching speeds. The dynamic operation allows the circuit to achieve high speed with fewer transistors by utilizing transient states and pre-charging techniques
Data Source
AI summary
A data register unit, a SAR ADC and an electronic device are disclosed. The data register unit comprises: a first high-speed flip-flop; a second high-speed flip-flop; and a first logic gate, wherein the first high-speed flip-flop and the second high-speed flip-flop comprise a high-speed flip-flop circuit respectively, which comprises: a first PMOS transistor, a first NMOS transistor, an inverter and a logic gate. The data register unit of the present disclosure is composed of a high-speed flip-flop circuit with a very simple structure and suitable for fast operation. In a further embodiment, the high-speed flip-flop circuit can combine the bit pulse to realize the capacitor switching based on the comparison result. This increases the operation speed of the SAR ADC while significantly reducing the number of transistors required to implement the EMCS logic.