Two-Step SAR ADC Error Compensation With Replica CDAC
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Solution Overview
Problem
Two-step successive approximation register (SAR) analog-to-digital converters face limitations in coarse ADC resolution due to sampling bandwidth mismatch and clock skew, with existing solutions either consuming excessive power or limiting conversion speed.
Innovation Solution
The proposed two-step SAR ADC modifies the search destination of the coarse SAR ADC during conversion using a down-scaled replica of the main CDAC to compensate for signal-dependent residual errors, reducing errors without adding a sample-and-hold amplifier or merging capacitive analog-to-digital converters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a two-step SAR ADC is used to improve conversion speed, then productivity is improved, but measurement precision deteriorates due to sampling bandwidth mismatch and clock skew
Solution Approach 1:
The patent creates a down-scaled replica of the main CDAC (capacitive digital-to-analog converter) to generate a compensation signal. This replica CDAC copies the structure and operation of the main CDAC but at a reduced scale, allowing it to track and compensate for errors introduced by sampling bandwidth mismatch and clock skew without requiring additional sample-and-hold amplifiers or merging of CDACs.
Solution Approach 2:
The patent implements a feedback mechanism where the compensation signal generated by the replica CDAC is fed back to correct the coarse ADC output. The replica CDAC continuously tracks the errors introduced during the two-step conversion process and provides real-time compensation, thereby maintaining high measurement precision while preserving the fast conversion speed benefits of the two-step architecture.
2Measurement precision
If existing error correction methods are applied to improve measurement precision, then measurement precision is improved, but device complexity increases due to additional sample-and-hold amplifiers or merged CDACs
Solution Approach 1:
The replica CDAC serves multiple functions simultaneously: it acts as a scaled-down version of the main CDAC for error tracking, generates the compensation signal for correction, and integrates seamlessly with the existing two-step SAR ADC architecture. This multi-functionality eliminates the need for separate sample-and-hold amplifiers or merged CDAC structures, thereby improving measurement precision without increasing device complexity.
3Measurement precision
If sampling bandwidth is increased to improve measurement precision, then measurement precision is improved, but use of energy increases
Solution Approach 1:
The patent changes the parameter of the replica CDAC by scaling it down relative to the main CDAC. This down-scaling reduces the capacitance values and associated power consumption while maintaining the ability to track and compensate for sampling errors. The compensation signal generated by this lower-power replica CDAC effectively corrects measurement precision without requiring increased sampling bandwidth that would consume more energy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances coarse ADC resolution by reducing errors associated with sampling bandwidth mismatch, improving conversion accuracy without increasing power consumption or reducing conversion speed.
Implementation Method 1
The sample-and-hold circuit is configured to sample an input signal to be digitized
Implementation Method 2
The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to an output terminal of the sample-and-hold circuit, and an output terminal coupled to a first input terminal of the comparator
Data Source
AI summary
An analog-to-digital converter (ADC) circuit includes a signal input terminal, a sample-and-hold circuit, and a successive approximation register (SAR) ADC. The sample-and-hold circuit includes an input terminal coupled to the signal input terminal. The SAR ADC includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to an output terminal of the sample-and-hold circuit, and an output terminal coupled to a first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal, an output terminal coupled to a second input terminal of the comparator.