Two-Step SAR ADC Error Correction With Replica CDAC Feedback
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Solution Overview
Problem
Two-step successive approximation register (SAR) analog-to-digital converters face limitations in coarse ADC resolution due to sampling bandwidth mismatch and clock skew, with existing solutions either consuming excessive power or limiting conversion speed.
Innovation Solution
The proposed two-step SAR ADC modifies the search destination of the coarse SAR ADC during conversion by using a down-scaled replica of the main CDAC to compensate for signal-dependent residual errors, reducing errors without adding a sample-and-hold amplifier or merging capacitive converters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a two-step SAR ADC is used to improve conversion speed, then conversion speed is improved, but coarse ADC resolution deteriorates due to sampling bandwidth mismatch and clock skew
Solution Approach 1:
The patent implements feedback by using the output of the main CDAC (which experiences bandwidth mismatch and clock skew) to dynamically adjust and correct the search destination in the coarse SAR ADC. This feedback mechanism compensates for the errors introduced by sampling bandwidth mismatch and clock skew, thereby maintaining high resolution despite the fast two-step conversion process.
Solution Approach 2:
The patent dynamically changes the search destination parameter of the coarse SAR ADC based on the actual output from the main CDAC. By adjusting this parameter in real-time during conversion, the system compensates for signal-dependent residual errors and maintains accurate resolution while operating at high conversion speeds.
2Measurement precision
If existing error correction methods are applied to improve coarse ADC resolution, then resolution is improved, but power consumption increases
Solution Approach 1:
The patent employs self-service by utilizing the existing main CDAC output signal to generate the error correction information needed for the coarse SAR ADC. Instead of adding separate correction circuits or components, the system uses its own operational output to compensate for its own errors, thereby improving resolution without significant additional power consumption.
3Measurement precision
If existing error correction methods are applied to improve coarse ADC resolution, then resolution is improved, but conversion speed is limited
Solution Approach 1:
The patent merges the error correction function with the main conversion process by integrating the correction mechanism directly into the two-step SAR ADC architecture. The correction is performed using the same conversion timing and signal paths, eliminating the need for separate correction stages that would slow down the conversion process.
4Device complexity
If capacitor size is reduced to improve integration density, then device complexity is reduced, but measurement precision deteriorates due to increased noise and error
Solution Approach 1:
The feedback mechanism dynamically compensates for errors that become more significant with smaller capacitor sizes. By continuously adjusting the search destination based on actual conversion results, the system compensates for noise and error effects that would otherwise be magnified by reduced capacitor dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances coarse ADC resolution by reducing errors associated with sampling bandwidth mismatch, improving conversion speed and power efficiency, and allows for a reduction in capacitor size, thereby enhancing overall performance.
Implementation Method 1
a first capacitive digital-to-analog converter (CDAC)... configured to sample the input signal to be digitized, and sample an output of the sample-and-hold circuit
Implementation Method 2
a second CDAC... configured to sample the input signal to be digitized
Implementation Method 3
The SAR ADC includes a comparator... The first CDAC is coupled to a first input of the comparator, and is configured to sample the input signal to be digitized
Data Source
AI summary
An analog-to-digital converter (ADC) circuit includes a signal input terminal, a sample-and-hold circuit, and a successive approximation register (SAR) ADC. The sample-and-hold circuit includes an input terminal coupled to the signal input terminal. The SAR ADC includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to an output terminal of the sample-and-hold circuit, and an output terminal coupled to a first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal, an output terminal coupled to a second input terminal of the comparator.