SAR ADC Timing Using Replica Level Shifters Across PVT Corners
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Solution Overview
Problem
The challenge in designing high-speed analog-to-digital converter (ADC) circuits lies in optimizing the bottom-plate level shifter delay (T_BP,LVL) across various process, voltage, and temperature (PVT) corners, which is crucial for maximizing speed and dynamic range while minimizing power consumption and avoiding functional failures due to mismatched input bandwidths and sampling instances in multi-stage ADCs.
Innovation Solution
The implementation of a replica circuit path that tracks the propagation delay of actual level shifters, using a combination of core and I/O domain devices, allows for adaptive timing adjustments without extensive process characterization, ensuring optimal speed and alignment of sampling instances across different PVT corners.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the bottom-plate level shifter delay is optimized for maximum speed, then the conversion speed increases, but the timing mismatch across PVT corners causes functional failures and increases power consumption
Solution Approach 1:
The patent employs a replica level shifter circuit that copies the timing characteristics of the actual level shifter. This replica circuit generates a delayed version of the control signal that accurately reflects the PVT-dependent timing variations, allowing the main circuit to maintain proper synchronization without extensive characterization across all PVT corners.
Solution Approach 2:
The delayed control signal from the replica level shifter is fed back to adjust the timing of operations in the main circuit. This feedback mechanism dynamically compensates for PVT variations, ensuring that sampling instances remain aligned across process, voltage, and temperature corners without requiring manual calibration.
2Manufacturing precision
If extensive process characterization is performed to optimize timing, then timing precision improves, but the design complexity and time-to-market increase
Solution Approach 1:
Instead of characterizing every PVT corner, the patent uses a replica level shifter that automatically copies the timing behavior of the actual circuit. This approach achieves high timing precision without requiring extensive manual measurement and characterization across all process, voltage, and temperature conditions.
Solution Approach 2:
The replica level shifter circuit is self-adjusting and automatically adapts to PVT variations without external intervention. The circuit generates its own timing compensation based on its inherent PVT-dependent behavior, eliminating the need for external characterization data or manual calibration procedures.
3Reliability
If the conversion time is increased to accommodate PVT variations, then timing alignment improves, but the conversion speed decreases
Solution Approach 1:
The patent dynamically adjusts the timing of control signals based on actual PVT conditions rather than using a fixed conservative timing margin. The replica level shifter continuously adapts its delay to match current process, voltage, and temperature conditions, allowing the circuit to operate at maximum speed while maintaining proper timing alignment.
Solution Approach 2:
The circuit changes its operational parameters dynamically by using the delayed control signal from the replica level shifter to adjust timing margins in real-time. This allows the conversion time to be optimized for each PVT corner without requiring a fixed increase in time that would degrade overall performance.
Data Source
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AI summary
A data converter circuit comprises timing circuitry configured to time stages of a conversion performed by the data converter circuit; a level shifter circuit configured to receive a control signal associated with the conversion and provide a level shifted version of the control signal to one or more switch circuits of the data converter circuit; and a time delay circuit element including a replica circuit of the level shifter circuit that adds a circuit delay to a transition of the control signal at the timing circuitry.