SAR ADC Timing With Replica Level Shifter Delay Tracking
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Solution Overview
Problem
Successive approximation register (SAR) analog-to-digital converter (ADC) circuits face challenges in achieving high speed and dynamic range while managing increasing complexity and power consumption, particularly due to variations in process, voltage, and temperature (PVT) corners, which affect the bottom-plate level shifter delay and synchronization between multi-stage ADCs.
Innovation Solution
The implementation of a replica circuit path that tracks the propagation delay of actual level shifters across PVT variations, minimizing unnecessary conversion time and aligning sampling instances between stages, reduces the need for extensive process characterization and trim settings, thereby optimizing speed and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If higher speed is demanded for SAR ADCs, then conversion speed improves, but timing synchronization becomes more difficult due to PVT variations
Solution Approach 1:
The patent uses a replica level shifter circuit that copies the delay characteristics of the actual level shifter. This replica circuit is used to generate timing signals that automatically track PVT variations, ensuring synchronization without requiring manual adjustment or characterization.
Solution Approach 2:
The timing circuitry uses the replica level shifter to create a feedback mechanism where the delay experienced by actual signals is automatically replicated and compensated for in timing control signals, maintaining synchronization under varying conditions.
2Manufacturing precision
If extensive process characterization and trim settings are implemented, then timing precision improves, but device complexity and power consumption increase
Solution Approach 1:
The replica level shifter circuit automatically adjusts its delay characteristics to match the actual level shifter under varying PVT conditions without requiring external trimming or characterization. The circuit self-calibrates through its design, eliminating the need for complex trim settings.
3Loss of time
If bottom-plate level shifter delay is reduced, then conversion time decreases, but synchronization between multi-stage ADCs deteriorates
Solution Approach 1:
The timing circuitry copies the delay characteristics of the level shifter using a replica circuit, allowing accurate timing predictions without adding physical delay. This enables tight timing control while maintaining synchronization across multiple ADC stages.
Data Source
AI summary
A data converter circuit comprises timing circuitry configured to time stages of a conversion performed by the data converter circuit; a level shifter circuit configured to receive a control signal associated with the conversion and provide a level shifted version of the control signal to one or more switch circuits of the data converter circuit; and a time delay circuit element including a replica circuit of the level shifter circuit that adds a circuit delay to a transition of the control signal at the timing circuitry.