Charge-Redistribution SAR ADC Reset Phasing for Lower Harmonic Distortion
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Solution Overview
Problem
Conventional charge-redistribution successive approximation register (SAR) analog-to-digital converters (ADCs) experience undesired harmonic distortion due to sample-dependent charge drawn from the reference voltage source, particularly in high-speed applications, as the output impedance of the reference voltage source is greater than zero, leading to increased power consumption when attempting to reduce this dependence.
Innovation Solution
The implementation of a charge-redistribution SAR ADC with a temporal offset in the reset process of its converter stages, where the switches are controlled to selectively connect capacitors to the reference voltage or ground, and the capacitors are weighted in capacitance, reducing the sample dependence of the total charge drawn from the reference voltage source throughout each conversion cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the output impedance of the reference voltage source is reduced to reduce sample dependence of charge, then harmonic distortion is reduced, but power consumption increases
Solution Approach 1:
The patent segments the reset operation into multiple phases by introducing a temporal offset between different converter stages. The reset process is divided into a first reset phase for a first subset of converter stages and a second reset phase for a second subset of converter stages, allowing charge to be drawn from the reference voltage source in a controlled, staggered manner that reduces sample dependence without requiring low output impedance
Solution Approach 2:
The patent applies preliminary action by performing the reset operation during the conversion process itself rather than waiting for a separate reset phase. The temporal offset is introduced while conversion is ongoing, allowing the DAC to continue converting the analog input signal while simultaneously resetting converter stages, thereby eliminating the need for additional reset time and reducing overall power consumption
2Object-affected harmful factors
If conventional simultaneous reset is used, then device complexity is low, but sample dependence of total charge drawn from reference voltage source remains high
Solution Approach 1:
The patent introduces dynamic control of the reset process by using a controller that selectively enables different converter stages at different times based on the conversion progress. The temporal offset is dynamically adjusted during the conversion cycle, with the controller monitoring the conversion state and activating reset phases accordingly, transforming a static simultaneous reset into a dynamic staged reset that reduces sample dependence
Solution Approach 2:
The patent applies periodic action by introducing a temporal offset that creates periodic phases of resetting different converter stages. The reset operation is divided into periodic intervals where different subsets of converter stages are reset at different times, creating a rhythmic pattern of charge drawing from the reference voltage source that reduces sample dependence while maintaining manageable circuit complexity
Data Source
AI summary
A charge redistribution SAR analog-to-digital converter includes a source of a reference voltage, a digital-to-analog converter, and a reset circuit. The digital-to-analog converter includes converter stages that range in significance from most significant to least significant. Each converter stage includes respective capacitors and switches. The switches are controllable to selectively connect the capacitors to the reference voltage or to ground. The capacitors of the converter stages are weighted in capacitance in accordance with significance of the converter stage. The reset circuit is to control the switches to reset the converter stages with a temporal offset between at least two of the converter stages. The temporal offset between the at least two of the converter stages reduces the dependence of the charge drawn from the reference voltage source during each conversion cycle on the sample of an analog input signal converted to a digital value during the conversion cycle.