SAR ADC Reset Skipping for Faster Low-Power Conversion
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Solution Overview
Problem
Current analog-to-digital converters (ADCs) face challenges in achieving high efficiency and low power consumption, particularly in portable devices where rapid technological advancements demand faster, smaller, and more efficient ADCs for wireless power transmission and communication systems.
Innovation Solution
The proposed ADC design incorporates a successive approximation register (SAR) architecture with a digital-to-analog converter (DAC) and capacitors, utilizing a path switching circuit to alternately change connections between the DAC and input terminals, allowing for efficient sampling and conversion of analog signals to digital signals, while minimizing power consumption by skipping unnecessary reset operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional SAR ADC performs reset operations in every conversion cycle, then the ADC maintains accurate conversion results, but power consumption increases and conversion speed decreases
Solution Approach 1:
The patent applies the skipping principle by selectively omitting reset operations in certain conversion cycles when they are not necessary for maintaining accuracy. The controller determines whether to perform reset operations based on previous conversion results and input signal characteristics, thereby skipping unnecessary resets to reduce power consumption and increase conversion speed while maintaining adequate conversion accuracy.
2Measurement precision
If the ADC performs reset operations in every conversion cycle, then conversion accuracy is maintained, but the conversion cycle time increases
Solution Approach 1:
The patent applies partial action by performing reset operations only when necessary rather than in every conversion cycle. The controller evaluates whether a reset is needed based on the previous conversion result and current input signal, performing the reset operation partially (selectively) to maintain adequate conversion accuracy while reducing the average conversion cycle time.
3Productivity
If the ADC is designed for high conversion speed, then productivity improves, but power consumption increases
Solution Approach 1:
The patent applies periodic action by implementing reset operations at selective intervals rather than continuously. The controller determines the timing of reset operations based on conversion needs, creating a periodic pattern where resets occur only when necessary. This reduces average power consumption while maintaining high conversion speed by avoiding continuous reset operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the ADC's efficiency and power management, enabling it to effectively convert analog signals to digital signals with reduced power usage, making it suitable for portable devices and wireless communication systems.
Implementation Method 1
a first capacitor group including a first set of capacitors connected to a first common node and a first control input terminal configured to receive digital control signals, and a second capacitor group including a second set of capacitors connected to a second common node
Data Source
AI summary
An analog-to-digital converter (ADC) is provided. The ADC may include an input terminal configured to receive input signals, a digital-to-analog converter (DAC), a first switch configured to control a connection between the DAC and the input terminal, a comparator, a second switch configured to control a connection between the DAC and the comparator, and a controller configured to control the first switch, the second switch, the DAC and the comparator.