Two-Bit SAR ADC Residual Voltage Scheme for Higher Resolution
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Solution Overview
Problem
Successive approximation analog-digital converters are limited to 10-bit resolution due to inaccuracies in voltage comparisons, which degrade digital precision, and increasing the number of bits beyond this does not significantly improve precision due to successive errors introduced at each iteration.
Innovation Solution
The proposed analog-digital converter architecture includes a first stage with a second means for comparing an intermediate voltage with a second voltage to generate a second bit, and a residual voltage calculation, which is applied back to the input or subsequent stages, allowing for improved precision and reduced power consumption and chip surface area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If successive approximation converters increase the number of conversion bits to achieve higher digital resolution, then measurement precision is improved, but conversion time increases proportionally with the number of iterations required
Solution Approach 1:
The converter is divided into multiple parallel one-bit converter stages, each handling a specific bit position. This segmentation allows simultaneous processing of multiple bits rather than sequential processing, thereby maintaining high digital resolution while reducing conversion time proportional to the number of parallel stages.
Solution Approach 2:
The invention transitions from a single-dimensional sequential processing approach to a multi-dimensional parallel processing architecture. By organizing converters in parallel stages with multiple processing paths, the system achieves higher resolution without linearly increasing conversion time, effectively adding a dimensional aspect to the conversion process.
2Measurement precision
If successive approximation converters increase the number of conversion bits to achieve higher digital resolution, then measurement precision is improved, but device complexity increases due to additional conversion stages
Solution Approach 1:
The complex high-resolution conversion task is segmented into multiple simpler one-bit conversion stages. Each stage handles a single bit position with dedicated comparator and capacitor, breaking down the overall complexity into manageable modular units that can be independently designed and tested.
Solution Approach 2:
The invention uses identical replicated one-bit converter units across multiple parallel stages. Each stage is a copy of the basic one-bit converter structure, which simplifies design verification and manufacturing. The replication of standardized modules reduces overall system complexity compared to designing a completely new multi-bit converter architecture.
3Measurement precision
If successive approximation converters use multiple iteration cycles to achieve high digital resolution, then measurement precision is improved, but power consumption increases due to repeated voltage comparisons and calculations
Solution Approach 1:
The power consumption is segmented and distributed across multiple parallel one-bit stages rather than concentrated in a single sequential process. Each stage performs a simple one-bit comparison with minimal energy expenditure, and the parallel architecture allows these low-power operations to occur simultaneously, reducing total power consumption compared to repeated full-resolution comparisons.
Solution Approach 2:
Each one-bit conversion stage uses simple, low-cost components (single comparator, single capacitor) that consume minimal energy for their brief operational lifetime in each conversion cycle. These simple stages are replaced or reset for each new conversion, avoiding the need for complex, high-power continuous operation in sequential architectures.
4Measurement precision
If successive approximation converters perform multiple voltage comparisons in sequence to achieve high digital resolution, then measurement precision is improved, but the surface area required on the chip increases
Solution Approach 1:
The chip area is segmented into multiple compact parallel stages, each requiring minimal space for its one-bit converter components. This segmentation allows efficient spatial utilization where each stage occupies a small, standardized area, and the total area scales more efficiently than sequential architectures that require large buffer spaces for intermediate voltage storage and multiple comparator circuits.
Solution Approach 2:
Multiple functional elements (comparators, capacitors, switches) are merged into compact integrated one-bit converter units that can be tightly packed on the chip. The parallel architecture allows these merged units to be arranged in space-efficient configurations, reducing the overall chip surface area compared to distributed sequential stages that require additional routing and buffer space.
Data Source
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Figure 5
AI summary
The analog-to-digital converter includes a first stage in which a voltage to be converted (Vin) is applied to the input of a first comparator (2). The first comparator (2) outputs a first digital result (Bi) representing the comparison between the voltage to be converted (Vin) and the reference voltage (Vref) on a first digital output. The first digital output is connected to a means (3) for calculating a first intermediate voltage (V1). A second comparator (5) compares the first intermediate voltage (V1) to the reference voltage (Vref) and outputs a second digital result (Bi+1) on a second digital output terminal. The second digital output terminal is connected to a second means for calculating a residual voltage as a function of the voltage to be converted (Vin), the first (Va) and second (Vb) digital results, and the first and second digital results (Bi, Bi+1).