Noise-Shaping SAR ADC Using Switched Residue Capacitors
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Solution Overview
Problem
Analog-to-digital converters (ADCs), particularly successive approximation ADCs, face challenges in reducing quantization noise and achieving efficient noise shaping without increasing the device's area, as existing noise shaping methods require large holding capacitors to maintain effective noise reduction.
Innovation Solution
The proposed solution involves an ADC system with a capacitive DAC, a comparator, and a SAR, utilizing a switching circuit and amplifying circuit to implement noise shaping by alternately using two capacitors to add and acquire residue voltages, reducing the need for a large holding capacitor and minimizing device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If large holding capacitors are used for noise shaping, then quantization noise is reduced, but device area increases
Solution Approach 1:
The patent divides the single large holding capacitor into multiple smaller capacitors (first capacitor, second capacitor, third capacitor, fourth capacitor) that are distributed across different operational phases. This segmentation allows the system to achieve the same noise shaping effect with smaller individual capacitor sizes, thereby reducing the total device area while maintaining quantization noise reduction performance.
Solution Approach 2:
The patent implements noise shaping through periodic switching operations where capacitors are alternately connected and disconnected in different phases (first phase, second phase, third phase, fourth phase). This periodic action allows the system to accumulate and process residue voltages over multiple cycles, achieving effective noise reduction without requiring large capacitors to be present simultaneously.
2Measurement precision
If large holding capacitors are used for noise shaping, then quantization noise is reduced, but power consumption increases
Solution Approach 1:
By segmenting the capacitor system into multiple smaller units that operate in different phases, the patent reduces the total capacitance value required at any given moment. Smaller capacitors have lower charge storage requirements and thus lower power consumption for the same noise shaping effect, directly addressing the power consumption issue.
Solution Approach 2:
The periodic switching and phasing of capacitor operations allows the system to process residue voltages incrementally over time rather than requiring all capacitors to be active simultaneously. This temporal distribution of operational load reduces the instantaneous power consumption while maintaining the cumulative noise shaping effect.
3Measurement precision
If complex noise shaping circuits are used, then quantization noise is reduced, but device complexity increases
Solution Approach 1:
The patent designs the capacitor network and switching circuitry to serve multiple functions: the same capacitors and switches are used for both noise shaping and for acquiring/processing residue voltages in different phases. This multi-functionality reduces the need for separate dedicated circuits, thereby limiting the increase in device complexity despite the advanced noise shaping capability.
Solution Approach 2:
The patent combines the noise shaping function with the residue voltage processing function into a unified capacitor-switching network. By merging these functions into a single integrated circuit structure rather than using separate circuits, the overall device complexity is reduced while still achieving effective quantization noise reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces quantization noise while maintaining efficient noise shaping without the need for large capacitors, thereby minimizing the ADC's area and power consumption.
Implementation Method 1
a first capacitor coupled between the first input of the comparator and the switching circuit
Implementation Method 2
a switching circuit, a first capacitor coupled between the first input of the comparator and the switching circuit
Implementation Method 3
an amplifying circuit having an input and an output, wherein the input of the amplifying circuit is coupled to the switching circuit
Data Source
AI summary
In certain aspects, an analog-to-digital converter (ADC) includes a comparator having a first input, a second input, and an output. The ADC also includes a digital-to-analog converter (DAC) coupled to the first input of the comparator, a switching circuit, a first capacitor coupled between the first input of the comparator and the switching circuit, a second capacitor coupled between the first input of the comparator and the switching circuit, and an amplifying circuit having an input and an output, wherein the input of the amplifying circuit is coupled to the switching circuit. The ADC further includes a first switch coupled between the output of the amplifying circuit and the DAC, and a successive approximation register (SAR) having an input and an output, wherein the input of the SAR is coupled to the output of the comparator, and the output of the SAR is coupled to the DAC.