SAR ADC Noise Shaping Through Residue Transfer and Dual DACs
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Solution Overview
Problem
Existing analog-to-digital converters (ADCs), particularly successive approximation register (SAR) ADCs, face challenges in reducing quantization noise without increasing size or complexity, often requiring large capacitors or complex filtering.
Innovation Solution
The proposed solution involves a SAR ADC with two capacitive DACs and a comparator, using a switch circuit to alternate between feedback and compare modes, and employing noise shaping by transferring residue voltage between conversion cycles using the amplifier, eliminating the need for large capacitors and complex filtering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional SAR ADC design is used, then the ADC structure is simple and power consumption is low, but quantization noise cannot be effectively reduced without increasing size or complexity
Solution Approach 1:
The patent divides the ADC operation into distinct phases (sampling phase and conversion phase) and uses two separate capacitive DACs (first and second capacitive DACs) to handle different functions. This segmentation allows the system to implement noise shaping without requiring a completely redesigned complex structure, maintaining modularity while achieving improved precision.
Solution Approach 2:
The patent changes the operational parameters of the capacitive DACs by switching between different connection configurations (first connection configuration and second connection configuration) controlled by switch circuits. This parameter change enables the same hardware structure to perform both noise shaping and normal conversion functions, reducing quantization noise without proportionally increasing device complexity.
2Measurement precision
If large capacitors are used to reduce quantization noise, then measurement precision improves, but device area increases
Solution Approach 1:
The patent employs periodic switching between the first and second capacitive DACs through switch circuits controlled by a clock signal. This periodic action enables noise shaping that reduces quantization noise without requiring permanently large capacitors, thereby reducing the overall device area while maintaining measurement precision.
Solution Approach 2:
The switch circuits and capacitive DACs serve multiple functions: they operate as standard DACs during normal conversion and as noise shaping elements during noise shaping mode. This multi-functionality eliminates the need for separate dedicated noise reduction components that would increase device area, achieving quantization noise reduction within the existing capacitor footprint.
3Measurement precision
If complex filtering is applied to reduce quantization noise, then measurement precision improves, but device complexity and power consumption increase
Solution Approach 1:
The patent implements a feedback mechanism where the output of the comparator is fed back to the input through the switch circuit and capacitive DAC during the sampling phase. This feedback loop enables noise shaping that reduces in-band quantization noise without requiring complex external filtering circuits, thereby avoiding additional power consumption while improving measurement precision.
Solution Approach 2:
The ADC system performs noise shaping using its own internal components (capacitive DACs, switch circuits, and comparator) without requiring external filtering hardware. The system serves its own noise reduction needs through the noise shaping mechanism, eliminating the power consumption that would be required for separate complex filtering stages.
4Measurement precision
If noise shaping with feedback is implemented, then in-band quantization noise is reduced and SQNR improves, but circuit complexity increases
Solution Approach 1:
The patent merges the noise shaping function with the existing SAR ADC structure by integrating the feedback mechanism into the capacitive DAC and switch circuit. Rather than adding a separate noise shaping circuit, the invention combines noise shaping operations with the normal conversion operations, achieving improved SQNR without proportionally increasing circuit complexity.
Solution Approach 2:
The patent uses dynamic switching between different connection configurations of the capacitive DACs through clock-controlled switch circuits. This dynamic reconfiguration allows the same circuit elements to serve different purposes (normal conversion vs. noise shaping) at different times, achieving improved SQNR without requiring permanently complex circuit structures.
Data Source
AI summary
In certain aspects, an analog-to-digital converter includes a first capacitive digital-to-analog converter (DAC), a second capacitive DAC, and a comparator including a first input, a second input, and an output. The analog-to-digital converter also includes a switch circuit including a first input coupled to the first capacitive DAC, a second input coupled to the second capacitive DAC, a first output coupled to the first input of the comparator, and a second output coupled to the second input of the comparator. The analog-to-digital converter further includes a first switch coupled between the output of the comparator and the first input of the comparator, and a successive approximation register (SAR) coupled to the output of the comparator, the first capacitive DAC, and the second capacitive DAC.