SAR ADC Resistive DAC Weighting for Higher Resolution
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Solution Overview
Problem
Existing CDAC-based SAR ADC circuitry has limited resolution due to challenges in accurate capacitance modeling and fabrication of small capacitors, leading to noise injection and suboptimal signal-to-noise ratio, with limited adjustability for optimal performance.
Innovation Solution
The implementation of a resistive DAC (RDAC) with a non-binary weighting system using a resistive potential divider and capacitor switches, allowing for adjustable voltage changes and capacitance ratios to enhance ADC resolution and noise performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If small capacitors are used in CDAC-based SAR ADC circuitry to achieve higher resolution, then ADC resolution is improved, but manufacturing precision deteriorates due to fabrication challenges and noise injection
Solution Approach 1:
The patent replaces the traditional capacitive weighting system with a resistive weighting system. Instead of using capacitors with different capacitance values (C, 2C, 4C, etc.), the invention uses resistors with different resistance values (R, 2R, 4R, etc.) to achieve the same binary-weighted functionality. This substitution eliminates the manufacturing challenges associated with precise small capacitor fabrication while maintaining the required resolution and weighting accuracy.
Solution Approach 2:
The patent changes the fundamental parameter used for weighting from capacitance to resistance. By transitioning from a capacitive DAC (CDAC) to a resistive DAC (RDAC), the system achieves equivalent functional performance without the fabrication constraints of small capacitors. The resistive approach allows for more robust and manufacturable hardware while preserving the ADC resolution through proper resistive divider design.
2Device complexity
If traditional binary-weighted capacitive DAC is used, then circuit simplicity is maintained, but adaptability deteriorates due to limited adjustability for optimal performance
Solution Approach 1:
The patent introduces dynamic adjustability to the resistive DAC by enabling switching between different resistive weight configurations. The system can dynamically reconfigure the resistive weights to support both binary-weighted operation and non-binary-weighted operation, allowing adaptation to different performance requirements while maintaining a relatively simple underlying circuit structure.
Solution Approach 2:
The resistive DAC circuit is designed to perform multiple functions: it can operate in traditional binary-weighted mode for standard ADC applications, and it can also operate in non-binary-weighted mode for optimized performance scenarios. This multi-functionality provides adaptability without significantly increasing circuit complexity, as the same resistive network supports both operating modes.
3Measurement precision
If non-binary weighting system is implemented with resistive DAC, then ADC accuracy is improved through better noise performance, but device complexity increases due to additional switching circuitry
Solution Approach 1:
The patent merges the weighting function and the switching function into a unified resistive network structure. The same resistive dividers and switches that establish the binary-weighted connections also enable non-binary-weighted configurations when reconfigured. This merging approach achieves the desired ADC accuracy improvement without proportionally increasing device complexity, as the additional functionality is integrated into the existing circuit framework rather than requiring completely separate circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves ADC accuracy and stability by avoiding the manufacturing difficulties of small capacitors, reducing noise, and allowing for trimming of weights for optimal performance, resulting in enhanced signal-to-noise ratio and resolution.
Implementation Method 1
at least one resistive potential divider connected between high and low reference voltage sources so as to provide a set of different voltage signals at tapping points defined therealong
Implementation Method 2
the successive-approximation control circuitry comprises at least two capacitors having first and second terminals, their first terminals being connected to a said comparator-input terminal
Data Source
AI summary
The present invention relates to analogue-to-digital converter (ADC) circuitry. In particular, the present invention relates to ADC circuitry configured to use successive approximation to arrive at a multi-bit digital value representative of an analogue input value.