SAR ADC Variable Sampling Capacitor for Resolution-Power Switching
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Solution Overview
Problem
Existing ADC circuits are typically designed for specific applications, making them costly and inefficient to adapt for multiple applications, and they consume excessive power due to fixed sampling capacitance, which degrades signal-to-noise ratio when scaled for different resolutions.
Innovation Solution
A configurable successive approximation register (SAR) ADC circuit with N weighted bit capacitors that can switch between high-resolution and low-resolution modes by adjusting sampling capacitance and disabling the most significant bit capacitors in low-resolution mode, reducing power consumption and enabling adaptability across various applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If ADC circuits are designed for a particular application with fixed sampling capacitance, then measurement precision is improved, but adaptability deteriorates and power consumption increases
Solution Approach 1:
The patent implements dynamic reconfiguration of the ADC circuit by enabling the sampling capacitor to be divided into multiple resolvable units that can be selectively activated. The most significant bit capacitor can be dynamically switched between sampling the input signal and sampling a common mode voltage, allowing the ADC to adapt its resolution and power consumption based on application requirements while maintaining measurement precision through controlled capacitor activation patterns
Solution Approach 2:
The patent changes the operational parameters of the ADC by introducing a control mechanism that dynamically adjusts the sampling capacitance configuration. By switching the most significant bit capacitor between different sampling modes (input signal vs. common mode voltage) and controlling which capacitors participate in the conversion process, the ADC can vary its effective resolution and power consumption to match different application needs
2Use of energy by stationary object
If sampling capacitance is reduced for lower resolution applications, then power consumption is reduced, but measurement precision deteriorates
Solution Approach 1:
The patent applies partial action by enabling only the necessary portion of the sampling capacitor array based on the required resolution. When full resolution is not needed, the most significant bit capacitor is used to sample common mode voltage rather than the full input signal, and fewer capacitors are activated during the conversion process, reducing power consumption while maintaining sufficient measurement precision for the application
Solution Approach 2:
The patent dynamically changes the effective sampling capacitance parameter by controlling which capacitors are activated and how they are configured during sampling and conversion. This allows the system to reduce power consumption by using smaller effective capacitance for lower resolution requirements while maintaining the ability to achieve full resolution when needed through complete capacitor array activation
3Measurement precision
If all weighted bit capacitors are used for sampling in high-resolution mode, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic control over capacitor activation based on the conversion requirements. During high-resolution conversions, all capacitors are activated to ensure maximum precision. For lower resolution requirements or between conversions, the most significant bit capacitor is dynamically switched to sample common mode voltage and fewer capacitors are activated, reducing sampling power consumption while maintaining the capability for high-precision measurements when needed
Data Source
AI summary
A successive approximation register analog-to-digital converter (SAR ADC) circuit comprises N weighted bit capacitors, wherein N is a positive integer greater than one; a sampling circuit configured to sample an input voltage onto the N weighted bit capacitors; and logic circuitry. The logic circuitry is configured to enable sampling of the input voltage onto the N weighted bit capacitors in a high-resolution mode; enable sampling of the input voltage onto N−M of the weighted bit capacitors in a low-resolution mode and sampling a common mode voltage onto the most significant M weighted bit capacitors, wherein M is a positive integer greater than zero and less than N; and initiate successive bit trials using the weighted bit capacitors to convert the sampled input voltage to a digital value.