SAR ADC Reference Ripple Compensation With Multi-Pulse Charge Splitting
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Solution Overview
Problem
High-resolution time-interleaved SAR ADCs face challenges in achieving high signal-to-noise distortion ratio (SNDR) and spurious-free dynamic range (SFDR) due to reference buffer ripples, which are exacerbated by process, voltage, and temperature changes, limiting design metrics such as speed, power, and chip area.
Innovation Solution
A reference charge compensation (RCC) circuit with multiple pulses compensation is used to split large peak charges into dual half-peak charges, allowing for enhanced timing tolerance and reduced compensation overshoot, effectively addressing reference ripple compensation in SAR ADCs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If calibration and/or compensation is utilized to decrease reference ripple, then SNDR and SFDR are improved, but the compensation becomes less effective under PVT changes and may even increase ripple in extreme corners
Solution Approach 1:
The patent implements dynamic tracking of reference ripple characteristics through continuous monitoring of voltage fluctuations during reset and conversion cycles. The compensation circuit adjusts its parameters in real-time based on detected ripple conditions, enabling adaptive compensation that maintains effectiveness across PVT variations rather than relying on fixed calibration values
Solution Approach 2:
The patent employs feedback mechanisms where the reference buffer output is monitored and the detected ripple information is fed back to adjust compensation parameters. This closed-loop approach allows the system to automatically adapt to changing conditions and maintain optimal compensation performance under varying process, voltage, and temperature conditions
2Measurement precision
If an error-correction scheme with additional conversion cycle is used, then resolution is improved and decoupling capacitors are reduced, but speed of the overall SAR ADC is limited
Solution Approach 1:
The patent merges the reference ripple compensation function with the existing SAR ADC conversion process by implementing compensation within the same conversion cycle. The compensation circuit operates concurrently with the normal conversion operations, eliminating the need for separate error correction cycles and maintaining high conversion speed while achieving improved resolution
3Manufacturing precision
If reference buffer is designed for high resolution, then linearity is improved, but power consumption and chip area increase
Solution Approach 1:
The patent extracts and compensates only the harmful ripple components from the reference buffer output rather than designing the entire reference buffer for high performance. By selectively removing the detrimental voltage fluctuations through compensation circuits, the system achieves high linearity without requiring the reference buffer itself to be oversized or high-power consuming
Data Source
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AI summary
An analog-to-digital converter (ADC) circuit includes a digital-to-analog converter (DAC) circuit, a comparator circuit, an encoder, and a compensation circuit. The DAC circuit receives a reference voltage and provides an output signal based on the reference voltage. The comparator circuit compares the output signal with an analog input signal and generates a comparison signal. A reset command is generated based on the output signal being greater than the analog input signal. The encoder splits a ripple associated with the reference voltage into multiple pulses in response to a reset command. The compensation circuit generates, responsive to the reset command, compensation pulses to compensate the multiple pulses.