Differential SAR ADC CDAC Topology for Reference Ripple Suppression
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Solution Overview
Problem
Existing SAR ADCs face challenges in reducing reference-voltage ripple, which degrades dynamic and static performance, particularly in time-interleaved ADCs, due to large decoupling capacitors required for high-speed operations, leading to increased chip area and power consumption, and cross-talk between sub-ADCs.
Innovation Solution
A SAR ADC with a differential CDAC topology and capacitive devices connected between input and reference voltage terminals to cancel leakage paths, reducing ripple and minimizing the need for large decoupling capacitors, thereby suppressing reference-voltage ripple and optimizing chip area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large decoupling capacitor is used to reduce reference-voltage ripple, then the ripple attenuation is improved, but the chip area and power consumption increase
Solution Approach 1:
The patent divides the single large decoupling capacitor into multiple smaller decoupling capacitors distributed across different reference voltage nodes (Vref+, Vref-, Vcm). This segmentation allows effective ripple attenuation at multiple points in the reference voltage network without requiring one large capacitor, thereby reducing overall chip area while maintaining reliability.
Solution Approach 2:
The patent introduces dummy switches as intermediary elements that provide alternative current paths during switching transitions. These dummy switches act as mediators that reduce the transient current burden on the reference voltage buffer, allowing smaller decoupling capacitors to achieve the same ripple attenuation effect that would otherwise require large capacitors.
2Reliability
If a large decoupling capacitor is used to reduce reference-voltage ripple, then the ripple attenuation is improved, but the power consumption increases
Solution Approach 1:
By segmenting the decoupling capacitance into multiple smaller capacitors distributed at different reference voltage nodes, the patent reduces the peak current demand on the reference voltage buffer. Each smaller capacitor handles a portion of the transient current, allowing the buffer to operate at lower power while achieving the same overall ripple attenuation performance.
Solution Approach 2:
The dummy switches serve as intermediaries that provide alternative current paths during CDAC switching events. By routing transient currents through these dummy switches rather than directly through the reference voltage buffer, the buffer's power consumption is reduced while the decoupling capacitors still effectively attenuate reference voltage ripple.
3Device complexity
If conventional CDAC topology is used without capacitive cancellation devices, then the circuit complexity is low, but cross-talk between sub-ADCs and memory effects occur
Solution Approach 1:
The patent introduces capacitive cancellation devices as intermediary elements that provide alternative current paths for input signals during switching transitions. These capacitors act as mediators that redirect leakage currents away from the reference voltage nodes, preventing cross-talk between sub-ADCs and memory effects without significantly increasing overall circuit complexity.
Solution Approach 2:
The patent acknowledges the unavoidable parasitic capacitance in MOSFET switches and converts this harmful effect into a beneficial one by adding capacitive cancellation devices. These devices exploit the switching behavior to create equal and opposite leakage paths, transforming the harmful cross-talk and memory effects into constructive interference that cancels out the unwanted signals.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces ripple and improves performance by canceling leakage paths, enhancing signal-to-noise ratio and spurious-free dynamic range, while minimizing chip area and power consumption.
Implementation Method 1
capacitive devices connected between input and reference voltage terminals to cancel leakage paths
Data Source
AI summary
A SAR ADC (50) is disclosed. It comprises a differential input port having a first input (VinP) configured to receive a first input voltage and a second input (VinN) configured to receive a second input voltage, of opposite polarity compared with first input voltage. Furthermore, it comprises a (300) having a first sub circuit (310P) comprising a first plurality of capacitors (2Cu, Cu), each connected to a common node (320P) of the first sub circuit (310P) with a first terminal, and a second sub circuit (310N) comprising a second plurality of capacitors (2Cu, Cu), each connected to a common node (320N) of the second sub circuit (310N) with a first terminal. For each capacitor (2Cu, Cu) of the first plurality of capacitors, the first sub circuit (310P) comprises a first switch (S4) connected between the first input (VinP) of the SAR ADC and a second terminal of that capacitor, a second switch (S2) connected between a first reference-voltage input (VrP) and the second terminal of that capacitor, a third switch (S1) connected between a second reference-voltage input (VrN) and the second terminal of that capacitor, and a capacitive device (XP) connected between the second input (VinN) of the SAR ADC and the second terminal of that capacitor. The second sub circuit is arranged in a similar way.