Oversampled SAR ADC With Rotating CDAC for Lower DNL Error
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Solution Overview
Problem
Analog-to-digital converters (ADCs) face challenges in reducing differential nonlinearity (DNL) errors due to component mismatches in their internal digital-to-analog converters (DACs), which affect the linearity of the ADC's output.
Innovation Solution
The proposed ADC employs an oversampled successive-approximation-register (SAR) architecture with a feedback DAC that includes both a resistive DAC (RDAC) and a capacitive DAC (CDAC). The CDAC incorporates rotation logic to rotate the intermediate DAC voltage across different capacitors during each conversion sub-phase, effectively canceling out component mismatches and reducing DNL errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional SAR ADC with a single DAC is used, then the device complexity is low, but the manufacturing precision deteriorates due to component mismatches in the DAC
Solution Approach 1:
The patent divides the n-bit DAC into two separate DACs: an m-bit CDAC (capacitive DAC) and an (n-m)-bit RDAC (resistive DAC). Each DAC handles a different portion of the digital code, with the CDAC processing the most significant bits and the RDAC processing the least significant bits. This segmentation allows each DAC to use optimized component structures, reducing the impact of component mismatches on overall DNL error while maintaining manageable device complexity.
Solution Approach 2:
The patent employs a composite DAC architecture that combines two different types of DACs (capacitive and resistive) into a single feedback system. The CDAC uses capacitor arrays while the RDAC uses resistor arrays, and their outputs are combined to form the complete DAC output voltage. This composite approach leverages the strengths of both capacitor-based and resistor-based DAC designs to achieve lower DNL error than either type alone could provide.
2Measurement precision
If the ADC resolution is increased, then the measurement precision improves, but the device complexity increases due to larger DAC component arrays
Solution Approach 1:
By segmenting the high-resolution n-bit DAC into an m-bit CDAC and an (n-m)-bit RDAC, the patent reduces the complexity of each individual component array. Instead of requiring a single large capacitor array with 2^n elements, the system uses two smaller arrays with 2^m and 2^(n-m) elements respectively. This segmentation makes the implementation of high-resolution ADCs more practical while maintaining measurement precision.
Solution Approach 2:
The patent substitutes the traditional single capacitor-array-based DAC with a hybrid system that replaces part of the capacitive structure with a resistive structure. The RDAC uses resistor arrays to generate voltage divisions, which are then combined with the CDAC output. This substitution reduces the complexity requirements for achieving high resolution, as resistor arrays can be more easily implemented with precise matching than large capacitor arrays.
Data Source
AI summary
An ADC includes a comparator to provide a comparator output responsive to an input voltage of the ADC and a DAC output voltage; a SAR circuit including a SAR that stores an n-bit digital code that is initialized at a beginning of a conversion phase of the ADC, where the SAR circuit is to update the digital code responsive to the comparator output, where an ADC output is responsive to the digital code at an end of the conversion phase; and a DAC to provide the DAC output voltage responsive to the digital code and a reference voltage. The DAC includes an m-bit CDAC and an (n-m)-bit RDAC to provide an intermediate voltage responsive to the n-m least-significant bits of the digital code and the reference voltage. The CDAC provides the DAC output voltage responsive to the m most-significant bits of the digital code, the intermediate voltage, and reference voltage.