Single-Channel Time-Interleaved SAR ADC for Sampling Mismatch
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Solution Overview
Problem
Existing single-channel SAR ADCs with time-interleaved sampling techniques face challenges in maintaining synchronized sampling moments across channels, leading to errors that vary with supply voltage, process, and temperature, making correction difficult and costly.
Innovation Solution
The proposed SAR ADC employs N capacitor arrays with weight capacitors and a compensation capacitor, along with switch arrays and a channel switch group, where the sampling switch operates at a first frequency and channel switches at a second frequency, ensuring unified sampling and successive approximation states to eliminate sampling moment mismatches and charge injection errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional multi-channel time-interleaved sampling is used to increase sampling speed, then sampling speed is improved, but sampling moment mismatch errors occur that vary with supply voltage, process, and temperature
Solution Approach 1:
The patent merges multiple channel sampling operations into a single-channel structure with time-interleaved capacitor arrays. Instead of using multiple independent sampling switches that operate simultaneously, the invention uses one sampling switch that sequentially connects to different capacitor arrays representing different channels, thereby eliminating sampling moment mismatch while maintaining high sampling speed.
Solution Approach 2:
The patent segments the sampling process into sequential time-interleaved operations. The single sampling switch sequentially connects to different capacitor arrays (C1, C2, ..., CN) in different time slots, effectively dividing the sampling function across multiple capacitive storage elements while using a unified switching mechanism that eliminates synchronization errors.
2Device complexity
If sampling moment mismatch occurs in multi-channel TIS, then correction circuits become more complex and costly, but sampling precision deteriorates
Solution Approach 1:
The patent extracts the sampling function from multiple channel-specific sampling switches and consolidates it into a single unified sampling switch. This removes the source of sampling moment mismatch errors, making correction circuits unnecessary and thereby reducing device complexity while maintaining high sampling precision.
3Speed
If charge injection from sampling switch is not eliminated, then sampling speed can be increased, but sampling precision deteriorates due to charge injection errors
Solution Approach 1:
The patent converts the harmful charge injection effect into a beneficial one by using the sampling switch to simultaneously perform sampling and charge redistribution. The charge injected by the sampling switch is redirected to the capacitor arrays in a controlled manner, and the subsequent connection to virtual ground allows this charge to be neutralized, thereby eliminating errors while maintaining high sampling speed.
Solution Approach 2:
The patent introduces virtual ground as an intermediary node between the sampling switch and the capacitor arrays. This virtual ground acts as a charge sink that absorbs the charge injection from the sampling switch, preventing it from affecting the sampled signal and thereby maintaining both high sampling speed and precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves sampling precision, reduces correction complexity, and enhances high-frequency performance by using a unified sampling switch and eliminating charge injection errors, allowing for increased sampling speed and better dynamic range compared to traditional techniques.
Implementation Method 1
N capacitor arrays, each comprising N−1 weight capacitors and a compensation capacitor
Data Source
AI summary
SAR ADC and sampling method based on single-channel TIS. The SAR ADC comprises: a capacitor array comprising a weight capacitor and a compensation capacitor, a first switch array, a second switch array, a channel switch group and a sampling switch; when in a sampling state: a lower plate of the weight capacitor is connected to an input voltage by means of the first switch array, and an upper plate of the capacitor array is connected to a common mode voltage by the sampling switch and the channel switch group; when in a successive approximation state: the lower plate of the weight capacitor is connected to a reference voltage by the second switch array. Input signals are sampled by using a unified to sampling switch, which solves the problem in the traditional technology that sampling moments are mismatched due to different sampling signals in each time-interleaved channel.