Successive Approximation ADC Search Interval for Lower Power
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Solution Overview
Problem
Analog-to-digital converters (ADCs) using successive approximation are power-consuming due to the high energy requirements of the comparator and capacitor charging/discharging processes, which limits their efficiency in low-power microcontroller-based systems.
Innovation Solution
An electronic device for analog-to-digital conversion that initializes a successive approximation register with a first digital value, restricting subsequent conversions to a search interval above or below this value, reducing the need for significant bit changes and thus lowering power consumption, while maintaining fast conversion speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional successive approximation ADC is used, then conversion precision is achieved, but power consumption is high
Solution Approach 1:
The patent applies preliminary action by initializing the SAR register with a first digital value from a previous conversion cycle before starting the current conversion. This pre-positioning of the register allows the conversion to start from a closer point to the expected result, reducing the number of bit decisions needed and thereby reducing power consumption while maintaining precision
Solution Approach 2:
The patent changes the initial parameter state of the SAR register from a conventional reset state (all zeros) to a non-zero first digital value based on previous conversion results. This parameter change enables faster convergence and reduced switching activity in the capacitor array, directly addressing the power consumption issue while preserving measurement precision
2Measurement precision
If full conversion range is searched, then measurement precision is ensured, but conversion time increases
Solution Approach 1:
By pre-loading the SAR register with a first digital value that represents a starting point close to the expected conversion result, the patent reduces the number of successive approximation steps needed. This preliminary positioning allows the system to achieve full precision with fewer clock cycles, thereby reducing conversion time without sacrificing measurement accuracy
3Measurement precision
If capacitor array is fully charged/discharged each cycle, then conversion accuracy is maintained, but power consumption increases
Solution Approach 1:
The patent changes the initial state parameter of the capacitor array from fully discharged (conventional reset) to a state corresponding to the first digital value. This parameter change reduces the voltage swing required during conversion, decreasing the charge/discharge current through the capacitors and directly reducing power consumption while maintaining the ability to achieve accurate conversion results
Data Source
AI summary
The invention includes a successive approximation register, a digital-to-analog converter, a comparator and a control stage. The control stage initially sets the successive approximation register to a first digital value. The digital-to-analog converter converts the digital value stored in the successive approximation register to an analog value. The comparator compares the converted digital value with an analog input value. The control stage restricts subsequent analog-to-digital conversion for the analog input value to a search interval above or below the first digital value depending on whether the analog input value is greater or lower than the converted analog value of the first digital value.