SAR ADC Comparator Ripple Cancellation With Shared Gate Capacitors
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Solution Overview
Problem
The conventional successive approximation register analog-to-digital converters (SARADC) face an increase in circuit scale due to the need for multiple capacitors to cancel ripple, especially as resolution increases, leading to inefficiencies.
Innovation Solution
The proposed solution involves a digital-to-analog converter generating a pair of analog signals, a comparator, logic circuit, and transistors with varying sizes, along with common capacitors and switches, to reduce circuit scale by canceling ripple without the need for multiple capacitors per bit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If four capacitors are arranged in every bit to cancel ripple, then ripple cancellation is achieved, but circuit scale increases as resolution increases
Solution Approach 1:
The patent merges the ripple cancellation function into a shared capacitor structure that is commonly used across all bits. Instead of having separate capacitors for each bit, a single capacitor is shared by all bits to generate the opposite-phase ripple signal, thereby reducing the total number of capacitors from 4N (where N is the number of bits) to just 1 shared capacitor.
Solution Approach 2:
The shared capacitor serves multiple functions: it is used by all bits for ripple cancellation and also functions as part of the common reference voltage structure. This multi-functional design eliminates the need for dedicated capacitors for each bit while maintaining effective ripple cancellation across the entire converter.
2Measurement precision
If multiple capacitors are used per bit for ripple cancellation, then comparison accuracy is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines multiple capacitor functions into a single shared capacitor, reducing the total component count from 4N capacitors to 1 shared capacitor. This merging approach maintains the necessary comparison accuracy through effective ripple cancellation while significantly reducing manufacturing costs associated with purchasing, placing, and testing numerous capacitors.
Solution Approach 2:
The patent changes the architectural parameter from multiple discrete capacitors to a single shared capacitor with enhanced connectivity. This parameter change in the circuit topology achieves the same ripple cancellation effect with fewer components, thereby reducing manufacturing complexity and cost.
3Reliability
If four capacitors and multiple switches are arranged in every bit, then ripple is canceled, but the number of components increases
Solution Approach 1:
The patent merges the capacitor array into a single shared capacitor and consolidates the switch network into a common switch structure that serves all bits. This reduces the total component count from O(N) capacitors and switches to a constant number of shared components, thereby minimizing the quantity of physical components while maintaining ripple cancellation effectiveness.
Solution Approach 2:
The shared capacitor and common switch structure serve universal functions for all bits simultaneously. The shared capacitor generates the opposite-phase ripple signal that is applied to all bits, and the common switches control the connection of this shared capacitor to the respective bit lines, eliminating the need for dedicated capacitors and switches for each bit.
Data Source
AI summary
To reduce a circuit scale in a successive approximation register analog to digital converter (SARADC) provided with a circuit that cancels a ripple. A digital-to-analog converter generates at least one of a pair of analog signals according to a predetermined control signal. A comparator compares the pair of analog signals and outputs a comparison result. A logic circuit generates a control signal on the basis of the comparison result. A plurality of switches opens and closes a path between one of a source and a drain of each of a plurality of positive-side transistors having different sizes and a plurality of negative-side transistors having different sizes and an output terminal of the comparator on the basis of the control signal. A positive-side common capacitor has one end connected to a node of a predetermined positive-side reference voltage, and has the other end connected in common to each of the gates of the plurality of positive-side transistors. A negative-side capacitor has one end connected to a node of a negative-side reference voltage lower than the positive-side reference voltage, and has the other end connected in common to the gates of each of the plurality of negative-side transistors.