SAR ADC Partial Conversion Using Skipped MSB Determination
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Solution Overview
Problem
Conventional SAR ADCs have low conversion rates and high power consumption, particularly when performing multiple conversions, due to the need for a fixed number of clock cycles per bit determination, which can be inefficient for stable input signals.
Innovation Solution
Implementing a partial mode in SAR ADC operations where the determination of certain bits is skipped based on previous conversion results, allowing for a reduced number of clock cycles by setting values of certain bits and determining only a portion of the digital data in subsequent conversions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional SAR ADC performs fixed number of clock cycles per bit conversion, then conversion accuracy is maintained, but conversion rate is low and current consumption is high
Solution Approach 1:
The patent implements dynamic operation modes (full mode and partial mode) that adjust the number of clock cycles based on input signal characteristics. In partial mode, when MSBs are known or can be inferred, the ADC performs fewer clock cycles (skipping determination of those MSBs), thereby dynamically reducing power consumption and increasing conversion rate while maintaining accuracy when needed.
Solution Approach 2:
The patent changes the operational parameters (number of clock cycles, mode of operation) based on the conversion requirements. By switching between full conversion (N clock cycles) and partial conversion (fewer than N clock cycles), the system optimizes the balance between conversion rate, power consumption, and accuracy for different operating conditions.
2Productivity
If SAR ADC performs full conversion for all bits, then measurement precision is maintained, but conversion rate decreases
Solution Approach 1:
The patent applies partial action by performing complete bit determination only when necessary (full mode), and using partial determination (skipping known MSBs) when possible (partial mode). This selective approach maintains measurement precision for the bits that need to be determined while improving conversion rate by skipping bits that are already known or can be inferred from previous conversions.
3Device complexity
If SAR ADC uses fixed conversion process, then reliability is maintained, but device complexity increases
Solution Approach 1:
The patent introduces dynamic mode switching (full mode/partial mode) that adapts the conversion process complexity based on operational requirements. The controller selectively enables partial mode when MSBs are known, reducing process complexity, while maintaining full mode for reliability when complete bit determination is required, thus balancing complexity and reliability dynamically.
Data Source
AI summary
A successive approximation register (SAR) analog-to-digital converter (ADC) may be used to generate a first digital data of N-bit and a second digital data of N-bit for an analog data. When the second digital data and the first digital data include a first sequence of most significant bits (MSBs) having same values, a third digital data of N-bit may be generated for the analog data using the SAR ADC in a partial mode. In the partial mode, the SAR ADC is configured to skip determining a second sequence of MSBs of the third digital data, and only determine remaining bits of the third digital data. When the second digital data and the first digital data do not include the first sequence of MSBs having same values, the SAR ADC operates in a full mode to determine every bit of the N-bit third digital data.