SAR ADC Small-Signal Mapping for Low-Spur Linearity
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Solution Overview
Problem
Successive approximation register (SAR) analog-to-digital converters (ADCs) face challenges in achieving ultra-low spurs levels and small signal linearity due to DAC cell mismatches, which limit their performance in radar systems, especially when dealing with weak reflection signals amidst strong ones.
Innovation Solution
The SAR ADC is designed with an adaptive conversion scheme that identifies small signal levels and skips initial conversion steps, using programmable thresholds to reduce the impact of mismatches in larger DAC cells, thereby enhancing small signal linearity and signal-to-noise ratio without compromising speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional SAR ADC conversion is used, then the ADC operates with standard conversion steps, but small signal linearity deteriorates due to DAC cell mismatches
Solution Approach 1:
The patent implements a dynamic conversion scheme where the ADC adapts its conversion steps based on the input signal amplitude. For small signals, the ADC skips initial conversion steps and adjusts the conversion process dynamically, allowing the system to optimize performance for different signal conditions rather than using a fixed conversion approach
Solution Approach 2:
The patent changes the conversion parameters (number of steps, threshold values) based on signal strength detection. By detecting whether the input signal is small or large and adjusting the conversion parameters accordingly, the system achieves better small signal linearity while maintaining overall conversion accuracy
2Measurement precision
If all conversion steps are executed for every signal, then conversion accuracy is maintained, but processing time increases unnecessarily for small signals
Solution Approach 1:
The patent applies partial action by executing only the necessary number of conversion steps based on signal strength. For small signals, fewer conversion steps are performed compared to the full conversion process, reducing processing time while maintaining sufficient accuracy through adaptive thresholding and signal detection mechanisms
3Speed
If larger DAC cells are used, then conversion speed is improved, but mismatch errors increase affecting small signal performance
Solution Approach 1:
The patent segments the conversion process into different phases based on signal strength. By dividing the conversion steps and applying different processing approaches for small versus large signals, the system can use larger DAC cells for speed-critical operations while compensating for their mismatch errors through adaptive conversion logic for small signal applications
Data Source
AI summary
A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: an analog input signal (410); an ADC core (414) configured to receive the analog input signal (410) and comprising: a digital to analog converter, DAC (430) located in a feedback path; and a SAR controller (418) configured to control an operation of the DAC (430), wherein the DAC (430) comprises a number of DAC cells, arranged to convert a digital code from the SAR controller (418) to an analog form; a digital signal reconstruction circuit (450) configured to convert the digital codes from the SAR controller (418) to a binary form; and an output coupled to the digital signal reconstruction circuit (450) and configured to provide a digital data output (460). The DAC (430) is configurable to support at least two mapping modes, including a small signal mapping mode of operation; and the SAR controller (418) is configured to identify when the received analog signal is a small signal level, and in response thereto re-configure the DAC (430) and the digital signal reconstruction circuit (450) to implement a small signal mapping mode of operation.