SAR ADC Split Dithering for Harmonic Spur Reduction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

High-performance and high-resolution analog to digital converters (ADCs) used in radio frequency (RF) signal conversion, particularly in 5G wireless base stations, face issues with harmonic spurs due to mismatch between successive approximation ADCs, which can't meet spurious-free dynamic range (SFDR) specifications despite calibration, necessitating improved nonlinearity error smoothing.

Innovation Solution

A split dithering approach is applied using two dither signals with different magnitudes, one for the most significant bits (MSB) and one for the least significant bits (LSB), to reduce harmonic spurs and nonlinearity errors in SAR ADCs, thereby enhancing the spurious-free dynamic range without unnecessary input signal dynamic range reduction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-generated harmful factors

If dithering is applied to smooth nonlinearity error in SAR ADC, then harmonic spurs are reduced, but input signal dynamic range is reduced

Engineering Contradiction:
Improveharmonic spursVSAvoidinput signal dynamic range
Core Design Contradiction:
Object-generated harmful factorsVSReliability

Solution Approach 1:

The dither signal is segmented into two distinct components: an MSB dither signal with larger magnitude for reducing prominent harmonic spurs, and an LSB dither signal with smaller magnitude for smoothing quantization noise without excessive dynamic range consumption. This segmentation allows each dither component to target specific frequency components efficiently.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different dither magnitudes are applied locally to different bit significance levels. The MSB dither operates with larger amplitude on the most significant bits where harmonic spurs dominate, while the LSB dither operates with smaller amplitude on least significant bits where quantization noise is more critical, optimizing the trade-off between spur reduction and dynamic range preservation.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If DAC calibration is performed to reduce mismatch errors, then some spurious-free dynamic range specification is met, but residual calibration errors remain insufficient

Engineering Contradiction:
ImproveDAC calibration accuracyVSAvoidspurious-free dynamic range
Core Design Contradiction:
Manufacturing precisionVSMeasurement precision

Solution Approach 1:

Instead of attempting to eliminate all mismatch errors through complex calibration procedures, the patent accepts the presence of residual calibration errors and uses dithering to convert these deterministic errors into randomized noise. This transformation allows the errors to be pushed into the noise floor rather than manifesting as distinct harmonic spurs, thereby improving spurious-free dynamic range.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The dither signal acts as an intermediary between the deterministic mismatch errors and the output spectrum. By adding this random signal, the deterministic error components are masked and redistributed across the frequency spectrum, preventing them from appearing as discrete spurious tones that would degrade SFDR performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP4439986A1Split-dithering scheme in successive approximation analog to digital converter
Publication Date: 2024.10.02 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • EP4439986A1 patent drawingFigure 1A
  • EP4439986A1 patent drawingFigure 1B
  • EP4439986A1 patent drawingFigure 1C~2B

AI summary

A system includes a dither generator module that includes a most significant bits (MSB) dither generator device that generates a first random value. The dither generator module also includes a least significant bits (LSB) dither generator device that generates a second random value. The system further includes a first digital to analog converter (DAC) that receives a sum of the first random value and the second random value and generates a dither signal based on the sum of the first random value and the second random value. The system also includes an analog to digital converter (ADC) that receives a sum of the dither signal and a sampled input signal and generates a first digitized signal. The system includes a subtraction module that subtracts the sum of the first random value and the second random value from the first digitized signal to produce a digitized output signal.