SAR ADC Capacitor Sub-Array Switching for Fast Low-Power Conversion
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Solution Overview
Problem
Existing 2-bit/step successive approximation (SAR) analog-to-digital converters (ADCs) require greater overall capacitance and consume more power compared to 1-bit/step SAR ADCs, necessitating a design that balances speed and capacitance usage.
Innovation Solution
A SAR ADC with three comparators and three capacitor sub-arrays, where each sub-array samples the analog input and adjusts reference levels based on previous conversion phase data to generate N-bit digital outputs, reducing overall capacitance and power consumption while maintaining fast conversion speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a 2-bit/step SAR ADC is used to increase conversion speed, then conversion speed is improved, but overall capacitance and power consumption increase
Solution Approach 1:
The capacitor array is divided into multiple sub-arrays (first, second, third, and fourth sub-arrays) with different capacitance values. Each sub-array is selectively connected to reference voltages during different conversion phases, allowing the ADC to achieve 2-bit/step conversion speed while using only a portion of the total capacitance at any given time, thereby reducing overall power consumption
Solution Approach 2:
The patent employs dynamic switching of capacitor connections through control signals that selectively connect different capacitor sub-arrays to reference voltages based on the current conversion phase. This dynamic reconfiguration allows the system to maintain fast 2-bit/step conversion while adapting capacitance usage to minimize power consumption during each conversion step
2Speed
If a 2-bit/step SAR ADC is used to increase conversion speed, then conversion speed is improved, but overall capacitance increases
Solution Approach 1:
The capacitor array is divided into multiple sub-arrays (first, second, third, and fourth sub-arrays) with different capacitance values. Each sub-array is selectively connected to reference voltages during different conversion phases, allowing the ADC to achieve 2-bit/step conversion speed while using only a portion of the total capacitance at any given time, thereby reducing overall capacitance requirement
Solution Approach 2:
The patent introduces a time dimension to the capacitance usage by operating in multiple conversion phases (first conversion phase, second conversion phase, etc.). Different capacitor sub-arrays are activated in different phases, effectively distributing the capacitance requirement across time rather than requiring all capacitances simultaneously, thus reducing the overall capacitance needed
Data Source
AI summary
A SAR ADC, used for converting an analog input into an N-bit digital output in a conversion phase, includes: three comparators, each two capacitor sub-arrays, coupled to the three comparators respectively, wherein the two capacitor sub-arrays are used for sampling the analog input and providing two inputs for the corresponding comparator; and an SAR logic, coupled to the three comparators and the three capacitor arrays, for, in each conversion sub-phase, coupling two selected capacitors of each capacitor sub-array to a set of determined reference levels, coupling two capacitors, which were selected in a preceding conversion sub-phase, of each capacitor sub-array to a set of adjusted reference levels obtained based on a set of data outputted from the three comparators in a preceding conversion sub-phase, and then generating two bits of the N-bit digital output by encoding a set of data outputted from the three comparators.