SAR ADC Sub-Capacitor Switching for Linearity Compensation
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Solution Overview
Problem
Conventional SAR analog-to-digital converters face challenges in achieving high capacitance accuracy and linearity due to capacitance mismatching, which affects the numeric accuracy of capacitive digital-to-analog converters.
Innovation Solution
The proposed solution involves a capacitive digital-to-analog conversion circuit with sub-capacitors that redistribute charges to update comparison voltages, allowing for self-linear compensation and effective elimination of level shifts caused by capacitance deviations, thereby improving the accuracy of bit determination in SAR analog-to-digital conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the capacitance or area of each capacitor is increased to improve capacitance accuracy and linearity, then the numeric accuracy of the capacitive digital-to-analog converter is improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The most significant bit conversion unit is divided into multiple sub-conversion units (first sub-conversion unit, second sub-conversion unit, etc.), each containing sub-capacitors. This segmentation allows the system to achieve high accuracy through coordinated operation of multiple smaller capacitor groups rather than requiring a single large high-precision capacitor, thereby reducing manufacturing complexity while maintaining capacitance accuracy.
Solution Approach 2:
The patent changes the operational parameters of the capacitive digital-to-analog converter by introducing sequential charge redistribution operations. The sub-capacitors are switched and redistributed in specific sequences during the conversion process, changing the temporal and operational parameters rather than relying solely on static capacitance values, which enables high accuracy without proportionally increasing device complexity.
2Reliability
If conventional capacitive digital-to-analog converters are used without charge redistribution mechanisms, then the device structure is simpler, but capacitance mismatching causes level shifts and reduces conversion accuracy
Solution Approach 1:
The patent implements a feedback mechanism through the SAR control circuit that monitors the conversion process and controls the switching of sub-capacitors based on comparison results. The charge redistribution operation is triggered and controlled based on feedback from the comparison unit, allowing the system to compensate for capacitance mismatching dynamically during conversion, thereby improving reliability while managing complexity through intelligent control.
Solution Approach 2:
The charge redistribution mechanism allows the capacitive digital-to-analog converter to self-correct for capacitance mismatching errors. The sub-capacitors automatically redistribute charges in response to control signals, enabling the system to eliminate level shifts caused by manufacturing variations without requiring external calibration or complex compensation circuits, thus improving reliability with moderate complexity increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the accuracy and linearity of SAR analog-to-digital conversion by enabling self-linear compensation for capacitance mismatching, resulting in improved bit determination and digital value conversion.
Implementation Method 1
the SAR control circuit is used to re-distributes the charges stored in at least the first sub-capacitor to the (N−2)-th sub-capacitor of the (N−1)-th conversion unit according to the (N−1)-th bit to update the comparison voltage
Data Source
AI summary
A successive approximation (SAR) analog-to-digital converter for generating a digital signal of N bits is provided. The converter includes a capacitive digital-to-analog conversion circuit including an (N−1)-th conversion unit to a first conversion unit. Each of the first conversion unit to the (N−2)-th conversion unit includes a capacitor. The (N−1)-th conversion unit comprises a number of sub-capacitors. Each of the sub-capacitors of the (N−1)-th conversion unit has substantially the same capacitance with corresponding capacitor of the first conversion unit to the (N−2)-th conversion unit. During the conversion process, the SAR control circuit, after generating the value of the most significant bit (MSB) of the digital signal, generates the value of the next bit by controlling the (N−1)-th conversion unit. Then, the SAR control circuit repeatedly uses at least one of the sub-capacitors of the (N−1)-th conversion unit to generate the value of other bits to perform self linear compensation.