SAR ADC Digital Error Correction with Redundant Sub-DACs
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Solution Overview
Problem
Successive Approximation (SAR) Analog to Digital Converters (ADCs) face limitations in conversion speed due to the requirement for sufficient settling time of the DAC output, leading to code decision errors, and existing error correction methods either increase hardware complexity or power consumption.
Innovation Solution
A digital error correction technique that uses multiple sub-DACs with shared elements, employing a binary decision algorithm to correct code errors by rearranging sub-DAC elements and using VCM and VREF as reference voltages, allowing for error correction without additional hardware, thereby reducing settling time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the DAC output settling time is extended to ensure accurate code decision, then the measurement precision is improved, but the conversion speed deteriorates
Solution Approach 1:
The patent applies preliminary action by performing error correction in advance through digital filtering of historical conversion results. The filter accumulates and processes past data to predict and correct potential errors before they affect the current conversion, allowing the DAC to use a shorter settling time while maintaining accuracy through proactive error compensation.
2Measurement precision
If digital error correction is implemented using conventional methods, then the code decision accuracy is improved, but the device complexity increases
Solution Approach 1:
The patent replaces complex hardware-based error correction mechanisms with a digital filtering algorithm that operates on historical conversion data. Instead of adding complex correction circuits or additional hardware components, the invention uses software-based digital signal processing to achieve error correction, thereby maintaining code decision accuracy while avoiding increased hardware complexity.
3Productivity
If the DAC settling time is reduced to increase conversion speed, then the productivity is improved, but the measurement precision deteriorates due to code decision errors
Solution Approach 1:
The patent implements feedback by continuously monitoring and filtering historical conversion results to detect patterns of errors. The digital filter uses past data to provide feedback about systematic errors, which are then corrected in real-time, allowing the system to maintain high conversion speed with reduced settling time while compensating for the resulting code decision errors through intelligent feedback-based correction.
Data Source
AI summary
An apparatus for digital error correction in a successive approximation (SAR) analog to digital converter (ADC) includes a binary weighted digital to analog converter (DAC) which can be virtually divided into multiple sub-DACs for redundancy insertion; and a comparator configured to compare the analog input with a DAC level corresponding to digital. The apparatus further includes a register and control logic unit configured to control a switching operation for DAC and to add output codes obtained from sub-DACs to output the added code as a final A/D converted code.