SAR ADC Sub-DAC Coupling With Multiple Sample Capacitors
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Solution Overview
Problem
Current SAR ADCs face challenges in maximizing sampling times and minimizing the size of electrical components, such as sampling capacitors, while maintaining effective signal conversion.
Innovation Solution
The implementation of a SAR ADC with multiple capacitor networks, including sampling and non-sampling capacitors, and a digital-to-analog converter (DAC) comprising sub-DACs, where the output of the sub-DACs is coupled to both sampling and non-sampling capacitors, allowing for a sampling phase and a conversion phase to optimize signal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If a single sampling capacitor is used in SAR ADC, then the component size is minimized, but the sampling time cannot be maximized and signal conversion effectiveness deteriorates
Solution Approach 1:
The patent divides the single sampling capacitor into multiple capacitor networks (first capacitor network, second capacitor network, etc.), where each network contains its own sampling capacitor. This segmentation allows parallel sampling operations across multiple capacitors, extending the effective sampling time while maintaining signal conversion precision through coordinated operation of all capacitor networks.
2Duration of action of moving object
If multiple capacitor networks are implemented in SAR ADC, then sampling time is maximized, but the size of electrical components increases
Solution Approach 1:
The patent merges multiple capacitor networks into a unified SAR ADC architecture where all capacitor networks share common control logic, switching mechanisms, and readout circuits. This merging approach allows parallel sampling with extended time duration while minimizing the increase in overall component size through resource sharing and integrated design.
Solution Approach 2:
Each capacitor network in the patent is designed to perform multiple functions: sampling during the sampling phase, holding the sampled value during conversion, and participating in the digital-to-analog conversion process. This multi-functionality reduces the need for separate dedicated components, thereby maximizing sampling time without proportionally increasing total component size.
3Area of stationary object
If sampling capacitor size is minimized, then component size is reduced, but sampling time cannot be maximized
Solution Approach 1:
The patent segments the total sampling capacitance requirement across multiple smaller capacitor networks instead of using one large capacitor. Each sampling capacitor can be minimized in size while the collective array of multiple capacitors achieves the required total capacitance, thereby reducing individual component size while enabling extended sampling time through parallel operation.
4Device complexity
If component duplication is reduced in SAR ADC, then device complexity is minimized, but signal conversion effectiveness deteriorates
Solution Approach 1:
The patent merges multiple capacitor networks into a unified architecture that shares common control logic, switching networks, and readout pathways. This merging reduces device complexity by eliminating redundant separate conversion paths while maintaining signal conversion effectiveness through coordinated operation of all capacitor networks within the integrated system.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for efficient sampling and conversion of analog signals into digital outputs, enabling smaller sampling capacitors and reduced component duplication, thereby enhancing sampling times and minimizing component size.
Implementation Method 1
each capacitor network of the plurality of capacitor networks has a sampling capacitor for sampling an analog input signal to the SAR ADC
Implementation Method 2
a digital-to-analog converter (DAC) comprising a plurality of sub-DACs
Implementation Method 3
an analog comparator configured to compare a sampled analog input signal of the SAR ADC to an output of the DAC
Data Source
AI summary
A SAR ADC may include a plurality of capacitor networks, wherein each capacitor network of the plurality of capacitor networks has a sampling capacitor for sampling an analog input signal to the SAR ADC and at least one non-sampling capacitor. The SAR ADC may also include a DAC including a plurality of sub-DACs including at least a first sub-DAC representing most significant bits of an output of the SAR ADC, wherein the output of the first sub-DAC is coupled to the sampling capacitors of the plurality of capacitor networks and a second sub-DAC representing bits of the output of the SAR ADC lesser in magnitude significance than those of the first sub-DAC, wherein the output of the second sub-DAC is coupled to a respective one of at least one non-sampling capacitor of each of the plurality of capacitor networks.