SAR ADC Sub-DAC Gain Trimming for Faster High-Precision Conversion
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Solution Overview
Problem
High-resolution successive-approximation-register analog-to-digital converters (SAR ADCs) face challenges with increased chip surface area and costs due to large capacitors, and conventional trimming methods increase conversion delay and power consumption while decreasing precision and maximum operating frequency.
Innovation Solution
A system with a gain trim module that selectively trims the gain of a sub capacitive digital-to-analog converter (DAC) based on accumulated error from the main capacitive DAC, reducing the need for trimming the sub DAC and allowing for faster conversion while decreasing size, power, and improving differential non-linearity (DNL).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional trimming methods are used on the main capacitive DAC, then manufacturing precision is improved, but conversion delay increases and maximum operating frequency decreases
Solution Approach 1:
The patent segments the trimming function by dividing the capacitive DAC into a main capacitive DAC and a sub capacitive DAC. The main DAC handles the majority of the conversion function, while the sub DAC is dedicated specifically to trimming operations. This segmentation allows trimming to be performed on a smaller, dedicated circuit rather than the entire DAC, reducing the impact on conversion speed while maintaining precision.
Solution Approach 2:
The sub capacitive DAC acts as an intermediary element that mediates between the main capacitive DAC and the trimming requirement. By introducing this intermediate trimming DAC, the system can adjust and calibrate the main DAC's performance without directly modifying the main DAC's structure or operation, thus preserving the main DAC's high-speed conversion capability while achieving precise trimming through the sub DAC.
2Manufacturing precision
If large capacitors are used in the SAR ADC, then manufacturing precision is improved, but chip surface area increases and costs increase
Solution Approach 1:
The patent segments the capacitive DAC into main and sub components with different capacitor size requirements. The main capacitive DAC uses smaller capacitors for high-speed operation, while the sub capacitive DAC uses larger capacitors specifically for trimming functions. This segmentation allows the system to achieve high precision without requiring all capacitors to be large, thus reducing overall chip area while maintaining conversion precision.
3Manufacturing precision
If trimming is performed to improve precision, then manufacturing precision is improved, but power consumption increases
Solution Approach 1:
The patent segments the trimming function into a dedicated sub capacitive DAC that operates independently from the main conversion process. This allows trimming operations to be performed selectively and efficiently on a smaller circuit, reducing the overall power consumption compared to trimming the entire DAC system. The sub DAC's smaller size and dedicated function enable precision improvement with lower power cost.
Data Source
AI summary
A system for a successive-approximation-register analog-to-digital converter (SAR ADC) includes a gain trim module and an SAR control module. The gain trim module is configured to selectively trim a gain of a sub capacitive digital-to-analog converter (DAC) of the SAR ADC. The SAR control module controls the gain trim module based on an accumulated error associated with a main capacitive DAC of the SAR ADC.