SAR ADC Capacitor-Line Calibration Using Swapped Voltage Patterns
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Solution Overview
Problem
High-resolution Successive Approximations Register (SAR) Analog-to-Digital Converters (ADCs) face challenges with capacitor mismatch, leading to missing codes, integral nonlinearity, and differential nonlinearity, which reduce the effective number of bits and are costly to calibrate due to the need for external components and high power consumption.
Innovation Solution
The technique calibrates SAR ADCs by measuring mismatch errors on the most significant bit capacitors using the same ADC's least significant bits, eliminating the need for external components and achieving calibration in the digital domain by adjusting weighting coefficients, thus increasing the effective resolution without requiring external predefined inputs or high-quality auxiliary ADCs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If capacitor size is increased to reduce mismatch errors, then measurement precision is improved, but area and power consumption increase
Solution Approach 1:
The ADC uses itself to measure its own capacitor mismatch errors by operating in calibration mode where the capacitive DAC is driven with test patterns and the ADC converts these patterns to digital values that reveal the mismatch errors, eliminating the need for external measurement equipment
Solution Approach 2:
The ADC switches between normal conversion mode and calibration mode by changing the control signals to the capacitive DAC, allowing the same hardware to serve dual purposes: normal operation and self-characterization of mismatch errors
2Measurement precision
If external auxiliary components are used to measure mismatch errors, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The ADC performs both its primary function of converting analog input signals to digital values and its secondary function of measuring its own capacitor mismatch errors using the same hardware components, making the system universal and eliminating the need for separate measurement equipment
Solution Approach 2:
The ADC characterizes its own internal capacitor mismatches by using its conversion mechanism to measure the errors, making the system self-diagnostic and eliminating dependency on external calibration equipment
3Measurement precision
If high-resolution auxiliary ADC is used to measure errors, then measurement precision is improved, but power consumption and area increase
Solution Approach 1:
The same ADC hardware is used for both normal signal conversion and for measuring capacitor mismatch errors, eliminating the need for a separate high-resolution auxiliary ADC and its associated power consumption
Solution Approach 2:
The ADC measures its own mismatch errors using its own conversion mechanism, making the system self-characterizing and eliminating the need for external high-precision measurement equipment that would consume additional power
4Measurement precision
If traditional calibration methods with external components are used, then measurement precision is improved, but productivity decreases
Solution Approach 1:
The ADC performs self-calibration by using its own conversion mechanism to measure mismatch errors and apply corrections, eliminating the need for external calibration equipment and manual calibration procedures
Solution Approach 2:
The control signals to the capacitive DAC are changed to switch between normal conversion mode and calibration mode, allowing the ADC to perform both functions using the same hardware with different operating parameters
Data Source
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Figure 3a
AI summary
The disclosure relates to a calibratable data converter, in particular to a calibratable Analog-to-Digital Converter (ADC) (300), comprising: a comparator (103); a first capacitor line (Cp, 110) comprising a plurality of capacitances coupled in parallel to a first input terminal (+) of the comparator (103); a second capacitor line (Cn, 120) comprising a plurality of capacitances coupled in parallel to a second input terminal (-) of the comparator (103); and a controller (104) configured: to drive a first part (111) of the first capacitor line (110) with a first voltage pattern (112) and a corresponding first part (121) of the second capacitor line (120) with a second voltage pattern (122) in order to sample the voltage patterns to the capacitors of the first part (111) of the first capacitor line (110) and the corresponding first part (121) of the second capacitor line (120) respectively, to drive the first part (111) of the first capacitor line (110) with a second voltage pattern (122)and the corresponding first part (121) of the second capacitor line (120) with the first voltage pattern (112) in order to generate a comparator input voltage (Vq) between the input terminals (+,-) of the comparator (103), and to adjust a second part (113) of the first capacitor line (110) and a corresponding second part (123) of the second capacitor line (120) in order to capture a residual voltage, which corresponds to the comparator input voltage (Vq), as calibration value.