SAR ADC Input Switch Timing for High-Impedance Sampling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In successive approximation type analog-to-digital conversion circuits, the short sampling time leads to large conversion errors due to insufficient charging of parasitic capacitance, especially when the impedance of external circuits like temperature sensors is high, and existing solutions like increasing switch transistor size or reducing sampling capacitance are limited by cost and complexity.
Innovation Solution
The introduction of a signal conversion circuit that generates a widened control signal to prolong the activation period of the analog input switch, allowing a longer charge time for parasitic capacitance, thereby reducing conversion errors while maintaining high-speed analog-to-digital conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the sampling time is shortened to achieve high-speed conversion, then the conversion speed is improved, but the charging time of parasitic capacitance becomes insufficient, leading to large conversion errors
Solution Approach 1:
The control switch is activated in advance before the analog input switch, performing preliminary charging of the parasitic capacitance. This preliminary action ensures that when the actual conversion begins, the capacitance is already charged, eliminating conversion errors while maintaining high conversion speed.
2Reliability
If the impedance of external circuits is increased to reduce loading effects, then the signal integrity is improved, but the charging time of parasitic capacitance increases, requiring longer sampling periods
Solution Approach 1:
The control switch performs preliminary charging of the parasitic capacitance before the actual conversion process. This allows external circuits to maintain high impedance for signal integrity while the capacitance is charged in advance during the control signal's activation period, eliminating the need to extend the sampling period.
3Measurement precision
If the size of switch transistors is increased to reduce parasitic capacitance effects, then the conversion accuracy is improved, but the device complexity and cost increase
Solution Approach 1:
The control switch acts as an intermediary element that enables accurate conversion without requiring large switch transistors in the analog input path. By introducing this additional control switch that activates beforehand, the system achieves the effect of reduced parasitic capacitance impact without increasing the size or complexity of the main signal path components.
4Loss of time
If the sampling capacitance is reduced to improve conversion speed, then the conversion time is shortened, but the charging capability of parasitic capacitance during sampling is insufficient
Solution Approach 1:
The control switch charges the parasitic capacitance in advance before the actual sampling occurs. This preliminary charging action allows the sampling capacitance to remain small for fast conversion while the parasitic capacitance is already charged when sampling begins, eliminating conversion errors without requiring larger sampling capacitance or longer sampling times.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces conversion errors and simplifies external circuits, achieving high-speed analog-to-digital conversion while minimizing cost and complexity, particularly for high-impedance input terminals.
Implementation Method 1
the time for charging the parasitic capacitance existing in the path between the analog input terminal to be converted and the input of the amplifier circuit to the potential of the analog input signal to be converted is about the sampling time of the sample-and-hold circuit
Implementation Method 2
Each of a plurality of analog signals input to a plurality of analog input terminals may be sequentially converted into a digital signal by a scanning operation
Data Source
AI summary
The semiconductor device according to this disclosure includes an analog input terminal, an amplifier circuit, a sample-and-hold circuit, an analog input switch connected between the analog input terminal and the input terminal of the amplifier circuit, a control switch connected between the output terminal of the amplifier circuit and the input terminal of the sample-and-hold circuit, a comparison circuit connected to the output terminal of the sample-and-hold circuit, an analog-to-digital converter connected to the comparator circuit, a control circuit, and a signal conversion circuit for converting the first control signal from the control circuit into a second control signal. The analog input switch is turned on during the activation level of the second control signal. The period of the activation level of the second control signal is longer than that of the first control signal to reduce a conversion error of an analog-to-digital conversion circuit.