SAR ADC Switchable Reference Voltage for Lower Power and Latency
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Solution Overview
Problem
Conventional SAR ADC architectures use reference voltages equal to the maximum input voltage, which affects power consumption and latency due to the number of clock cycles required for conversion.
Innovation Solution
A successive approximation register (SAR) analog to digital converter (ADC) design that utilizes a voltage reference generator to selectively connect capacitors to either a ground voltage or a reference voltage, allowing the SAR logic to generate digital input words based on comparator output voltages, thereby determining the digital output word by comparing the analog input voltage with the reference voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If reference voltage is set equal to maximum input voltage, then measurement precision is maintained, but power consumption increases and conversion latency increases
Solution Approach 1:
The patent dynamically changes the reference voltage parameter based on the input voltage range. Instead of using a fixed reference voltage equal to the maximum input voltage, the system adjusts the reference voltage to match the actual input signal amplitude, thereby reducing power consumption while maintaining conversion precision for the given input range.
Solution Approach 2:
The reference voltage is made dynamic rather than static. The system can switch between different reference voltage levels (e.g., full-scale reference or reduced reference) depending on the input signal characteristics, allowing the CDAC to operate at lower power when full-scale reference is not required while maintaining accurate conversion.
2Measurement precision
If reference voltage is set equal to maximum input voltage, then measurement precision is maintained, but conversion latency increases due to more clock cycles required
Solution Approach 1:
By changing the reference voltage parameter to match the actual input signal range, the system reduces the number of approximation steps needed in the SAR converter. When the input signal occupies only a portion of the full scale, using a reduced reference voltage concentrates the approximation steps within the actual signal range, reducing conversion latency while maintaining precision.
3Use of energy by moving object
If reference voltage is reduced to optimize power consumption, then power consumption decreases, but measurement precision may be compromised
Solution Approach 1:
The system dynamically adapts the reference voltage to the input signal characteristics. When power saving is needed and the input signal is small, a reduced reference voltage is used, which maintains precision for that specific input range while reducing power consumption. The SAR converter adjusts its approximation process accordingly to maintain accuracy.
Solution Approach 2:
The reference voltage parameter is changed based on operating conditions. The system can select between full-scale reference (for maximum precision when needed) and reduced reference (for power savings when input signals are small), with the SAR logic adapting its operation to maintain conversion accuracy regardless of the reference voltage level used.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and latency by optimizing the reference voltage usage, enabling efficient digital conversion with reduced clock cycles while maintaining accurate representation of the analog input voltage.
Implementation Method 1
a capacitor connected to the second input terminal of the comparator, and a second switch connected to the capacitor and selectively connected to either of a ground voltage and the reference voltage
Data Source
AI summary
An ADC is disclosed. The ADC includes a SAR logic circuit, a DAC, a comparator, and a voltage generator. The voltage generator includes a first switch connected to the comparator configured to selectively connect a second input terminal of the comparator to a reference voltage, a capacitor connected to the second input terminal of the comparator, and a second switch connected to the capacitor and selectively connected to either of a ground voltage and the reference voltage. The second switch is configured to selectively connect the capacitor to either of the ground voltage and the reference voltage, and the SAR logic circuit is further configured to receive the comparator output voltage, and to generate a digital input word for the DAC based on one or more comparator output voltages received from the comparator.