Segmented SAR ADC Capacitor Array for Lower Switching Error
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The mismatch and error in the digital-to-analog converter capacitor array (CDAC) of successive approximation register analog-to-digital converters (SAR ADCs) lead to non-linear conversion and reduced accuracy, particularly at the 28 nm process dimension, due to the large number of unit capacitances switched during binary code transitions, which complicates the design and calibration processes.
Innovation Solution
A capacitor array is designed with a control logic generation circuit, a control code logic conversion circuit, a first sub-capacitor array for low-order bits, and a second sub-capacitor array for high-order bits, where the second sub-capacitor array has equal capacitances and uses a thermometer code to control switching, reducing errors by ensuring only one unit capacitance is switched per bit change, and the first sub-capacitor array has binary weighted capacitances to minimize parallel branches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If binary weighted capacitor array is used for CDAC, then conversion speed is improved, but mismatch and error increase leading to reduced conversion accuracy
Solution Approach 1:
The capacitor array is segmented into two distinct sub-arrays: a first sub-capacitor array with binary weighted capacitances for low-order bits, and a second sub-capacitor array with equal capacitances for high-order bits. This segmentation allows each sub-array to optimize for its specific function, reducing overall mismatch and error while maintaining conversion speed.
Solution Approach 2:
Different regions of the capacitor array are assigned different capacitance characteristics tailored to their specific bit ranges. The first sub-capacitor array uses binary weighted capacitances optimized for low-order bits, while the second sub-capacitor array uses equal capacitances optimized for high-order bits, thereby reducing mismatch and conversion errors in each respective region.
2Adaptability or versatility
If large number of unit capacitances are switched during binary code transitions, then conversion range is expanded, but conversion errors increase due to non-linear conversion
Solution Approach 1:
The capacitor array is divided into two sub-arrays with different capacitance configurations. The first sub-capacitor array handles low-order bits with binary weighted capacitances, while the second sub-capacitor array handles high-order bits with equal capacitances. This segmentation reduces the number of capacitances switched during transitions and minimizes conversion errors.
Solution Approach 2:
The capacitance values are changed according to the bit position and significance. Low-order bits use binary weighted capacitances that scale with significance, while high-order bits use equal capacitances. This parameter change strategy reduces switching errors and improves conversion accuracy across the full conversion range.
3Area of moving object
If process dimension is reduced to 28 nm for small size, then device integration is improved, but mismatch and error become more serious affecting ADC performance
Solution Approach 1:
The capacitor array is segmented into two sub-arrays with different capacitance configurations optimized for their respective bit ranges. This segmentation reduces mismatch and error effects that become more pronounced at 28 nm process dimension, thereby maintaining conversion accuracy in small-sized devices.
Solution Approach 2:
Different regions of the capacitor array are assigned different capacitance characteristics suitable for their specific functions. The first sub-capacitor array uses binary weighted capacitances for low-order bits, while the second sub-capacitor array uses equal capacitances for high-order bits, reducing local mismatch and error effects at 28 nm scale.
Data Source
AI summary
The present disclosure relates to a capacitor array for an analog-to-digital converter, a successive approximation register analog-to-digital converter and a capacitor array board. The capacitor array includes a control logic generation circuit, a control code logic conversion circuit, a first sub-capacitor array and a second sub-capacitor array configured to form different regions of a high-order bit region and a low-order bit region. In the present disclosure, the capacitances of the second capacitor units are equal, so that the second capacitor units can be sequentially switched. Thus, no matter which bit in the second binary code changes, it will not cause a large number of the second capacitor units to switch together, thereby reducing conversion error. In addition, the capacitor array is divided in regions, which avoids the problem of a large number of parallel branches in case where only the second sub-capacitor array is arranged.