Split-Capacitor SAR ADC Switching to Reduce Nonlinearity Errors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Successive approximation register (SAR) analog-to-digital converters (ADCs) suffer from nonlinearity errors due to capacitance mismatches in capacitor arrays, leading to reduced accuracy and performance, particularly in mobile and portable devices.
Innovation Solution
The proposed solution involves a 3-bit split-capacitor type SAR ADC with two capacitor arrays and selection circuits, where a control logic circuit switches reference voltages between different levels in a uniform sequence during sampling stages to reduce voltage errors and nonlinearity errors, using a combination of capacitors with varying capacitances to reset the arrays and improve conversion accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If capacitor arrays are used in SAR ADC for low power consumption, then power efficiency is improved, but capacitance mismatch causes nonlinearity errors and reduces conversion accuracy
Solution Approach 1:
The capacitor array is divided into multiple sub-capacitor arrays (first capacitor array, second capacitor array, etc.), each handling a portion of the conversion process. This segmentation allows individual arrays to use fewer capacitors with better matching characteristics, reducing nonlinearity errors while maintaining the overall functionality and low power consumption of the ADC system.
2Measurement precision
If multiple capacitor arrays with different capacitance values are used, then conversion accuracy is improved through error cancellation, but device complexity increases
Solution Approach 1:
Multiple capacitor arrays are combined in a systematic configuration where their individual transfer curves are merged through uniform switching. The first capacitor array, second capacitor array, and additional arrays are integrated with their respective selection circuits to form a unified conversion system that achieves error cancellation while managing complexity through structured design.
Solution Approach 2:
The system employs dynamic switching between different capacitor arrays using selection circuits controlled by control logic. This dynamic reconfiguration allows the ADC to adaptively select and combine capacitor arrays based on the conversion requirements, enabling error cancellation through multiple transfer curves while maintaining operational flexibility and managing circuit complexity.
Data Source
AI summary
A method of operating an analog-to-digital converter includes in a first sampling stage, switching a swap signal to a first level for a first selection circuit to reset a first capacitor array according to a first voltage configuration and for a second selection circuit to reset a second capacitor array according to the first voltage configuration, and in a second sampling stage, switching the swap signal to a second level for the first selection circuit to reset the first capacitor array according to the second voltage configuration and for the second selection circuit to reset the second capacitor array according to the second voltage configuration. A control logic circuit is used to switch the swap signal between the first level and the second level in a uniform order in a plurality of sampling stages.