SAR ADC Capacitor Array Using Thermometer-Coded MSBs
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Solution Overview
Problem
Existing analogue-to-digital converters, particularly those using successive approximation register (SAR) architecture with binary weighted capacitive DACs, consume significant energy due to the charging and discharging of large capacitors, especially when determining the most significant bit, which is inefficient and leads to high power consumption.
Innovation Solution
The proposed solution involves using a digital-to-analogue converter with a combination of equal capacitors for determining the most significant bits via a thermometer coded signal and binary weighted capacitors for the remaining bits, employing a slope search algorithm to minimize energy loss by avoiding the discharge of large capacitors, and splitting binary DACs into sub-DACs to reduce capacitor mismatch risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If binary weighted capacitive DAC is used for SAR ADC, then the conversion accuracy is improved, but the power consumption increases significantly due to charging and discharging of large capacitors
Solution Approach 1:
The patent segments the binary weighted capacitive DAC into multiple sub-DACs, each with smaller capacitors. The MSB sub-DAC uses capacitors of size C, while LSB sub-DACs use progressively smaller capacitors. This segmentation allows the system to maintain the required conversion accuracy through combined output while avoiding the need to charge and discharge a single large capacitor, thereby reducing power consumption significantly.
Solution Approach 2:
The patent applies different capacitor sizes to different bit positions locally. The MSB sub-DAC uses larger capacitors (size C) appropriate for its resolution requirement, while LSB sub-DACs use smaller capacitors proportional to their bit weight. This local optimization ensures each sub-DAC operates with minimally sized capacitors for its specific function, reducing overall energy consumption while maintaining global conversion accuracy.
2Measurement precision
If large capacitors are used in MSB portion of DAC, then the reference signal accuracy is improved, but the energy required to charge and discharge capacitors increases
Solution Approach 1:
The patent divides the DAC into MSB sub-DAC with capacitors of size C and LSB sub-DACs with smaller capacitors. The MSB sub-DAC generates the reference signal with sufficient accuracy using only capacitors of size C, without requiring additional large capacitors. This segmentation enables the system to achieve the required reference signal accuracy while minimizing the total capacitance that needs to be charged and discharged, thereby reducing energy dissipation.
Solution Approach 2:
The patent changes the capacitor size parameter across different sub-DACs based on their bit position. The MSB sub-DAC uses capacitors of size C, while subsequent sub-DACs use progressively smaller capacitors (C/2, C/4, etc.). This parameter optimization ensures that each sub-DAC uses the minimum necessary capacitance for its resolution requirement, reducing the energy required for charging and discharging operations.
3Speed
If binary weighted capacitors are used in DAC, then the conversion speed is improved, but the capacitor mismatch due to process variations increases
Solution Approach 1:
The patent segments the binary weighted capacitor array into multiple sub-DACs. Each sub-DAC contains capacitors of similar size (MSB sub-DAC has capacitors of size C, LSB sub-DACs have progressively smaller capacitors). This segmentation reduces the relative impact of process variations because capacitors of similar size within each sub-DAC have better matching characteristics, while still maintaining the overall binary weighted functionality for fast conversion.
Solution Approach 2:
The patent optimizes capacitor matching locally within each sub-DAC by using capacitors of similar size within each group. The MSB sub-DAC uses capacitors of size C with better matching, while LSB sub-DACs use smaller capacitors appropriate to their bit weight. This local optimization of capacitor quality within each sub-DAC improves overall matching accuracy while maintaining the speed benefits of the binary weighted architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption by minimizing the energy required to charge and discharge capacitors, achieving lower overall energy dissipation and improving the efficiency of the analogue-to-digital conversion process while maintaining accuracy.
Implementation Method 1
a comparator for comparing the input signal with a reference signal and producing a comparator output signal
Implementation Method 2
the digital-to-analogue converter at least comprises a first portion implemented with equal capacitors
Data Source
AI summary
An analogue-to-digital (A/D) converter converts an analogue input signal to a digital code representing the analogue input signal. The A/D converter includes a comparator for comparing the input signal with a reference signal, a search logic block for determining the digital code, and an A/D converter arranged for receiving input from the search logic block and for providing the reference signal to be applied to the comparator. At least a first portion of the A/D converter is implemented with equal capacitors and may be controlled by a thermometer coded signal. Additionally, the A/D converter may include a second portion implemented using binary weighted capacitors controlled by a thermometer coded or binary coded signal. The A/D converter may also include a plurality of A/D converters coupled by an analogue addition circuit or a weighted summing amplifier.