SAR ADC Timer Calibration for Metastability Error Control
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Solution Overview
Problem
The stability of successive approximation register analog-to-digital converters (SAR ADCs) is compromised due to mismatches between comparison time and delay time caused by process, voltage, and temperature variations, leading to potential metastability errors and failure in generating digital codes within the allotted time.
Innovation Solution
A calibration method and circuit that adjusts the timer delay time based on probability calculations derived from repeated comparison operations, specifically turning off the timer in initial comparisons and adjusting the delay time during the final comparison operation corresponding to the least significant bit, to align the comparison time with the delay time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the timer delay time is fixed based on typical comparison time, then the SAR ADC can operate normally under typical conditions, but the stability deteriorates under process, voltage, and temperature variations causing mismatch between comparison time and delay time
Solution Approach 1:
The patent performs preliminary calibration of the timer delay time before normal operation. The calibration process measures the actual comparison time of the comparator and adjusts the timer delay time in advance to match, so that when PVT variations occur during operation, the timer is already configured to accommodate the actual comparison time, preventing metastability errors.
Solution Approach 2:
The patent implements a feedback mechanism where the calibration circuit measures the actual comparison time and uses this information to adjust the timer delay time. The system continuously monitors and adjusts the delay time based on the measured comparison time, ensuring that the timer delay time remains synchronized with the comparator's actual performance under varying conditions.
2Reliability
If the timer delay time is increased to accommodate worst-case comparison time, then metastability errors are reduced, but the conversion time increases and productivity decreases
Solution Approach 1:
The patent dynamically adjusts the timer delay time parameter based on the actual comparison time measurements. Instead of using a fixed conservative delay time that would slow down all conversions, the system calibrates and sets the delay time to match the actual comparison time, allowing optimal conversion speed while preventing metastability errors.
3Measurement precision
If calibration is performed for all N comparison operations, then the timing accuracy is improved, but the calibration complexity and time consumption increase
Solution Approach 1:
The patent extracts and focuses calibration on only the critical final comparison operation (Nth comparison) that corresponds to the least significant bit, rather than calibrating all N comparison operations. This selective approach targets the most timing-sensitive operation, achieving sufficient timing accuracy while significantly reducing calibration complexity and time consumption.
Data Source
AI summary
A calibration circuit and calibration method for a successive approximation register analog-to-digital converter (SAR ADC) are disclosed. The SAR ADC includes a comparator and generates a digital code. The calibration method includes the following steps: (a) creating a voltage difference between two inputs of the comparator, with the absolute value of the voltage difference being smaller than or equal to the absolute value of the voltage corresponding to the least significant bit (LSB) of the digital code; (b) updating a count value according to whether a timer of the SAR ADC issues a time-out signal, the timer issuing the time-out signal after a delay time has elapsed; (c) repeating steps (a) through (b) a predetermined number of times; (d) calculating a probability based on the predetermined number of times and the count value; and (e) adjusting the delay time according to the probability.